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| 型號(hào)： | OR2T04A-6BA84 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 63/192頁(yè) |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2T04A-6BA84 |
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Lucent Technologies Inc.
63
Data Sheet
June 1999
ORCA Series 2 FPGAs
Estimating Power Dissipation
(continued)
P
CLK
= [0.69 mW/MHz + (0.38 mW/MHz – Branch)
(20 Branches)
+ (0.022 mW/MHz – PFU) (150 PFUs)
+ (0.006 mW/MHz – SMEM_PFU)
(16 SMEM_PFUs)] [40 MHz]
= 427 mW
P
TTL
= 20 x [2.2 mW + (0.17 mW/MHz x 20 MHz
x 20%)]
= 57 mW
P
CMOS
= 20 x [0.17 mW x 20 MHz x 20%]
= 13 mW
P
OUT
= 30 x [(30 pF + 8.8 pF) x (5.25)
2
x 20 MHz
x 20%]
=128 mW
P
BID
= 16 x [(50 pF + 8.8 pF) x (5.25)
2
x 20 MHz
x 20%]
= 104 mW
TOTAL
= 1.50 W
OR2TxxA
The total operating power dissipated is estimated by
summing the standby (I
DDSB
), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respec-
tively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
P
T
=
Σ
P
PLC
+
Σ
P
PIC
The internal operating power is made up of two parts:
clock generation and PFU output power. The PFU out-
put power can be estimated based upon the number of
PFU outputs switching when driving an average fan-out
of two:
P
PFU
= 0.08 mW/MHz
For each PFU output that switches, 0.08 mW/MHz
needs to be multiplied times the frequency (in MHz)
that the output switches. Generally, this can be esti-
mated by using one-half the clock rate, multiplied by
some activity factor; for example, 20%.
The power dissipated by the clock generation circuitry
is based upon four parts: the fixed clock power, the
power/clock branch row or column, the clock power dis-
sipated in each PFU that uses this particular clock, and
the power from the subset of those PFUs that is config-
ured in either of the two synchronous modes (SSPM or
SDPM). Therefore, the clock power can be calculated
for the four parts using the following equations:
OR2T04A Clock Power
P
= [0.29 mW/MHz
+ (0.10 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T04A clock power
≈
1.8 mW/MHz.
OR2T06A Clock Power
P
= [0.30 mW/MHz
+ (0.11 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T06A clock power
≈
2.4 mW/MHz.
OR2T08A Clock Power
P
= [0.31 mW/MHz
+ (0.12 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T08A clock power
≈
3.2 mW/MHz.
OR2T10A Clock Power
P
= [0.32 mW/MHz
+ (0.14 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T10A clock power
≈
4.0 mW/MHz.
OR2T12A Clock Power
P
= [0.33 mW/MHz
+ (0.15 mW/MHz – Branch) (# Branches)
+ (0.01 mW/MHz – PFU) (# PFUs)
+ (0.003 mW/MHz – SMEM_PFU)
(# SMEM_PFUs)] fCLK
For a quick estimate, the worst-case (typical circuit)
OR2T12A clock power
≈
4.9 mW/MHz.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2T04A-6BA84I | Field-Programmable Gate Arrays |
| OR2T04A-6BC100 | Field-Programmable Gate Arrays |
| OR2T04A-6BC100I | Field-Programmable Gate Arrays |
| OR2T04A-6BC144 | Field-Programmable Gate Arrays |
| OR2T04A-6BC144I | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 1100pF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Solder Coated SnPb; Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: R Failure Rate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2T04A-6BA84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-6BC100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-6BC100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-6BC144 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-6BC144I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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