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參數(shù)資料
| 型號(hào)： | OR2T04A-6BA208I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 138/192頁(yè) |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2T04A-6BA208I |
Data Sheet
June 1999
ORCA Series 2 FPGAs
138
Lucent Technologies Inc.
Timing Characteristics
(continued)
Note: Speed grades of -5, -6, and -7 are for OR2TxxA devices only.
5-3226(F).r4
Figure 55. Read Operation—Flip-Flop Bypass
5-3227(F).r4
Figure 56. Read Operation—LUT Memory Loading Flip-Flops
Table 35A. OR2CxxA and OR2TxxA Asynchronous Memory Read Characteristics (MA/MB Modes)
OR2CxxA Commercial: V
DD
= 5.0 V ± 5%, 0 °C
≤
T
A
≤
70 °C; OR2CxxA Industrial: V
DD
= 5.0 V ± 10%, –40 °C
≤
T
A
≤
+85 °C.
OR2TxxA Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C
≤
T
A
≤
70 °C; OR2TxxA Industrial: V
DD
= 3.0 V to 3.6 V, –40 °C
≤
T
A
≤
+85
°C.
Parameter
Symbol
Speed
Unit
-2
-3
-4
-5
-6
-7
Min Max Min Max Min Max Min Max Min Max Min Max
Read Operation (T
J
= 85 °C, V
DD
= min):
Read Cycle Time
Data Valid after Address (A[3:0], B[3:0] to F[3:0])
Read Operation, Clocking Data into Latch/Flip-flop
(T
J
= 85 °C, V
DD
= min):
Address to Clock Setup Time (A[3:0], B[3:0] to CK)
Clock to PFU Out (CK to Q[3:0])—Register
T
RC
MEM*_ADEL
5.1
—
—
4.0
3.6
—
—
2.8
2.7
—
—
2.1
2.4
—
—
1.7
2.3
—
—
1.4
2.0
—
—
1.3
ns
ns
MEM*_ASET
REG_DEL
2.4
—
—
2.4
1.8
—
—
2.0
1.2
—
—
1.9
1.1
—
—
1.5
1.0
—
—
1.3
1.0
—
—
1.0
ns
ns
Table 35B. OR2TxxB Asynchronous Memory Read Characteristics (MA/MB Modes)
OR2TxxB Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C
≤
T
A
≤
70 °C; OR2TxxB Industrial: V
DD
= 3.0 V to 3.6 V, –40 °C
≤
T
A
≤
+85
°C.
Parameter
Symbol
Speed
Unit
-7
-8
Min
Max
Min
Max
Read Operation (T
J
= 85 °C, V
DD
= min):
Read Cycle Time
Data Valid after Address (A[3:0], B[3:0] to F[3:0])
Read Operation, Clocking Data into Latch/Flip-flop
(T
J
= 85 °C, V
DD
= min):
Address to Clock Setup Time (A[3:0], B[3:0] to CK)
Clock to PFU Out (CK to Q[3:0])—Register
T
RC
MEM*_ADEL
1.9
—
—
1.3
1.8
—
—
1.0
ns
ns
MEM*_ASET
REG_DEL
0.9
—
—
1.0
0.8
—
—
1.0
ns
ns
A[3:0], B[3:0]
F[3:0]
MEM*_ADEL
T
RC
A[3:0], B[3:0]
CK
MEM*_ASET
REG_DEL
Q[3:0]
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