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| 型號： | OR2T04A-5S160I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 44/192頁 |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2T04A-5S160I |
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Data Sheet
June 1999
ORCA Series 2 FPGAs
44
Lucent Technologies Inc.
Configuration Data Format
(continued)
Using ORCAFoundry
to Generate
Configuration RAM Data
The configuration data defines the I/O functionality,
logic, and interconnections. The bit stream is gener-
ated by the development system. The bit stream cre-
ated by the bit stream generation tool is a series of 1s
and 0s used to write the FPGA configuration RAM. The
bit stream can be loaded into the FPGA using one of
the configuration modes discussed later. In the bit
stream generator, the designer selects options which
affect the FPGA’s functionality. Using the output of the
bit stream generator, circuit.bit, the development sys-
tem’s download tool can load the configuration data
into the ORCA series FPGA evaluation board from a
PC or workstation. Alternatively, a user can program a
PROM (such as the ATT1700A Series Serial ROM or a
standard EPROM) and load the FPGA from the PROM.
The development system’s PROM programming tool
produces a file in .mks or .exo format.
Configuration Data Frame
A detailed description of the frame format is shown in
Figure 39. The header frame begins with a series of 1s
and a preamble of 0010, followed by a 24-bit length
count field representing the total number of configura-
tion clocks needed to complete the loading of the
FPGAs. Following the header frame is an optional ID
frame. This frame contains data used to determine if
the bit stream is being loaded to the correct type of
ORCA FPGA (i.e., a bit stream generated for an
OR2C15A is being sent to an OR2C15A). Since the
OR2CxxA devices are bit stream compatible with the
ATT2Cxx, ATT2Txx, OR2TxxA, and OR2TxxB families,
a bit stream from any of these devices will not cause an
error when loaded into an OR2CxxA, OR2TxxA, or
OR2TxxB device. The ID frame has a secondary func-
tion of optionally enabling the parity checking logic for
the rest of the data frames.
The configuration data frames follow. Each frame starts
with a 0 start bit and ends with three or more 1 stop
bits. Following each start bit are four control bits: a pro-
gram bit, set to 1 if this is a data frame; a compress bit,
set to 1 if this is a compressed frame; and the opar and
epar parity bits (see Bit Stream Error Checking). An
11-bit address field that determines in which column
the FPGA is to be written is followed by alignment and
write control bits. For uncompressed frames, the data
bits needed to write one column in the FPGA are next.
For compressed frames, the data bits from the previous
frame are sent to a different FPGA column, as speci-
fied by the new address bits; therefore, new data bits
are not required. When configuration of the current
FPGA is finished, an end-of-configuration frame (where
the program bit is set to 0) is sent to the FPGA. The
length and number of data frames and information on
the PROM size for the Series 3 FPGAs are given in
Table 7.
Table 7. Configuration Frame Size
Devices
OR2C/
2T04A
OR2C/
2T06A
OR2C/
2T08A
OR2C/
2T10A
OR2C/
2T12A
OR2C/
2T15A/B
OR2C/
2T26A
OR2C/
2T40A/B
# of Frames
480
568
656
744
832
920
1096
1378
Data Bits/Frame
110
130
150
170
190
210
250
316
Configuration Data
(# of frames x # of data bits/frame)
52,800
73,840
98,400
126,480
158,080
193,200
274,000
435,448
Maximum Total # Bits/Frame
(align bits, 1 write bit, 8 stop bits)
136
160
176
200
216
240
280
344
Maximum Configuration Data
(# bits x # of frames)
65,280
90,880
115,456
148,800
179,712
220,800
306,880
474,032
Maximum PROM Size (bits)
(add 48-bit header, ID frame, and
40-bit end of configuration frame)
65,504
91,128
115,720
149,088
180,016
221,128
307,248
474,464
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相關(guān)代理商/技術(shù)參數(shù) |
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| OR2T04A-5S208 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A5S208-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 400 LUT 152 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T04A-5S208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-5S84 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-5S84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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