![](http://datasheet.mmic.net.cn/370000/OR2T04A-2PS84_datasheet_16726875/OR2T04A-2PS84_97.png)
Data Sheet
June 1999
ORCA Series 2 FPGAs
Lucent Technologies Inc.
97
B10
C10
D10
A9
B9
C9
D9
A8
B8
C8
A7
B7
A6
C7
B6
A5
D7
C6
B5
A4
C5
B4
A3
D5
C4
B3
B2
A2
C3
A1
D4
D8
D13
D17
H4
H17
N4
N17
U4
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
—
PT1D
PT1C
PT1B
—
—
—
PT1A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5A
PT4D
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6A
PT5C
PT5A
PT4D
PT4A
PT3D
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
PT1C
PT1B
PT1A
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
PT7A
PT6C
PT6A
PT5D
PT5A
PT4D
PT4A
PT3D
PT3A
PT2D
PT2A
PT1D
PT1C
PT1B
PT1A
I/O
I/O
I/O-V
DD
5
I/O-D2
I/O-D1
I/O
I/O
I/O-D0/DIN
I/O
I/O
I/O
I/O-DOUT
I/O
I/O
I/O
I/O-TDI
I/O
I/O-V
DD
5
I/O
I/O-TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TCK
RD_DATA/TDO
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
RD_DATA/TDO
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
RD_DATA/TDO
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
RD_DATA/TDO
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
RD_DATA/TDO
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
RD_DATA/TDO
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Pin Information
(continued)
Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B
256-Pin PBGA Pinout
(continued)
Pin
2C/2T06A Pad
2C/2T08A Pad
2C/2T10A Pad
2C/2T12A Pad
2C/2T15A/B Pad
Function
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-V
DD
5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to V
DD
5 for the OR2TxxA series.
The pins labeled V
SS
-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.