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| 型號(hào)： | OR2T04A-4BC144I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 1000pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Solder Coated SnPb; Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: M Failure Rate |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 57/192頁(yè) |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2T04A-4BC144I |
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Lucent Technologies Inc.
57
Data Sheet
June 1999
ORCA Series 2 FPGAs
Special Function Blocks
(continued)
ORCASeries TAP Controller (TAPC)
The ORCA Series TAP controller (TAPC) is a 1149.1
compatible test access port controller. The 16 JTAG
state assignments from the IEEE1149.1 specification
are used. The TAPC is controlled by TCK and TMS.
The TAPC states are used for loading the IR to allow
three basic functions in testing: providing test stimuli
(Update-DR), test execution (Run-Test/Idle), and
obtaining test responses (Capture-DR). The TAPC
allows the test host to shift in and out both instructions
and test data/results. The inputs and outputs of the
TAPC are provided in the table below. The outputs are
primarily the control signals to the instruction register
and the data register.
Table 13. TAP Controller Input/Outputs
The TAPC generates control signals which allow cap-
ture, shift, and update operations on the instruction and
data registers. In the capture operation, data is loaded
into the register. In the shift operation, the captured
data is shifted out while new data is shifted in. In the
update operation, either the instruction register is
loaded for instruction decode, or the boundary-scan
register is updated for control of outputs.
The test host generates a test by providing input into
the ORCA Series TMS input synchronous with TCK.
This sequences the TAPC through states in order to
perform the desired function on the instruction register
or a data register. Figure 50 provides a diagram of the
state transitions for the TAPC. The next state is deter-
mined by the TMS input value.
5-5370(F)
Figure 50. TAP Controller State Transition Diagram
Symbol
I/O
Function
TMS
TCK
PUR
I
I
I
I
Test Mode Select
Test Clock
Powerup Reset
BSCAN Reset
Test Logic Reset
Select IR (high); Select DR (low)
Test Data Out Enable
Capture/Parallel Load DR
Capture/Parallel Load IR
Shift Data Register
Shift Instruction Register
Update/Parallel Load DR
Update/Parallel Load IR
PRGM
TRESET
Select
Enable
Capture-DR
Capture-IR
Shift-DR
Shift-DR
Update-DR
Update-IR
O
O
O
O
O
O
O
O
O
SELECT-
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
1
1
1
0
0
0
RUIDLE
1
TERESET
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
1
1
0
0
0
0
0
0
1
0
1
1
1
0
1
1
0
0
0
0
1
1
1
0
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