- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383706 > OR2C40A-3J432I (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號(hào)： | OR2C40A-3J432I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 22/192頁 |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2C40A-3J432I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁
22
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 2 FPGAs
Programmable Logic Cells
(continued)
PLC Architectural Description
Figure 23 is an architectural drawing of the PLC which
reflects the PFU, the lines, and the CIPs. A discussion
of each of the letters in the drawing follows.
A
. These are switching lines which give the router flexi-
bility. In general switching theory, the more levels of
indirection there are in the routing, the more routable
the network is. The switching lines can also connect
to adjacent PLCs.
The switching lines provide direct connections to
PLCs directly to the top, bottom, left, and right, with-
out using other routing resources. The ability to dis-
able this connection between PLCs is provided so
that each side of these connections can be used
exclusively as switching lines in their respective
PLC.
B
. These CIPs connect the X1 routing. These are
located in the middle of the PLC to allow the block to
connect to either the left end of the horizontal X1 line
from the right or the right end of the horizontal X1
line from the left, or both. By symmetry, the same
principle is used in the vertical direction. The X1
lines are not twisted, making them suitable for data
paths.
C
. This set of CIPs is used to connect the X1 and X4
nets to the switching lines or to other X1 and X4
nets. The CIPs on the major diagonal allow data to
be transmitted from X1 nets to the switching lines
without being scrambled. The CIPs on the major
diagonal also allow unscrambled data to be passed
between the X1 and X4 nets.
In addition to the major diagonal CIPs for the X1
lines, other CIPs provide an alternative entry path
into the PLC in case the first one is already used.
The other CIPs are arrayed in two patterns, as
shown. Both of these patterns start with the main
diagonal, but the extra CIPs are arrayed on either a
parallel diagonal shifted by one or shifted by two
(modulo the size of the vertical bus (5)). This allows
any four application nets incident to the PLC corner
to be transferred to the five switching lines in that
corner. Many patterns of five nets can also be trans-
ferred.
D
. The X4 lines are twisted at each PLC. One of the
four X4 lines is broken with a CIP which allows a sig-
nal to be routed a distance of four PLCs in any direc-
tion on a single line without an intermediate CIP The
X4 lines are less populated with CIPs than the X1
lines to increase their speed. A CIP can be enabled
to extend an X4 line four more PLCs, and so on.
For example, if an application signal is routed onto
HX4[4] in a PLC, it appears on HX4[5] in the PLC to
the right. This signal step-up continues until it
reaches HX4[7], two PLCs later. At this point, the
user can break the connection or continue the signal
for another four PLCs.
E
. These symbols are bidirectional buffers (BIDIs).
There are four BIDIs per PLC, and they provide sig-
nal amplification as needed to decrease signal
delay. The BIDIs are also used to transmit signals on
XL lines.
F
. These are the BIDI and BIDIH controllers. The 3-
state control signal can be disabled. They can be
configured as active-high or active-low indepen-
dently of each other.
G
.This set of CIPs allows a BIDI to get or put a signal
from one set of switching lines on each side. The
BIDIs can be accessed by the switching lines. These
CIPs allow a nibble of data to be routed though the
BIDIs and continue to a subsequent block. They also
provide an alternative routing resource to improve
routability.
H
.These CIPs are used to take data from/to the BIDIs
to/from the XL lines. These CIPs have been opti-
mized to allow the BIDI buffers to drive the large load
usually seen when using XL lines.
I
. Each latch/FF can accept data: from an LUT output;
from a direct data input signal from general routing;
or, as in the case of PLCs located in the two rows
(columns) adjacent to PICs, directly from the pad. In
addition, the LUT outputs can bypass the latches/
FFs completely and output data on the general rout-
ing resources. The four inputs shown are used as
the direct input to the latches/FFs from general rout-
ing resources. If the LUT is in memory mode, the
four inputs WD[3:0] are the data input to the mem-
ory.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2T04A-3J84 | Field-Programmable Gate Arrays |
| OR2T04A-3J84I | Field-Programmable Gate Arrays |
| OR2T04A-3PS144 | Field-Programmable Gate Arrays |
| OR2T04A-3PS144I | Field-Programmable Gate Arrays |
| OR2T04A-3PS160 | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C40A3PS208I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A3PS240I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A3PS304I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C40A4BC432-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述: |
| OR2C40A4PS208-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3600 LUT 342 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。