
Data Sheet
ORCA Series 2 FPGAs
June 1999
98
Lucent Technologies Inc.
U8
VSS
U13
VSS
U17
VSS
B1
VDD
D6
VDD
D11
VDD
D15
VDD
F4
VDD
F17
VDD
K4
VDD
L17
VDD
R4
VDD
R17
VDD
U6
VDD
U10
VDD
U15
VDD
W3
—
No Connect
J10
VSS
VSS—ETC
J11
VSS
VSS—ETC
J12
VSS
VSS—ETC
J9
VSS
VSS—ETC
K10
VSS
VSS—ETC
K11
VSS
VSS—ETC
K12
VSS
VSS—ETC
K9
VSS
VSS—ETC
L10
VSS
VSS—ETC
L11
VSS
VSS—ETC
L12
VSS
VSS—ETC
L9
VSS
VSS—ETC
M10
VSS
VSS—ETC
M11
VSS
VSS—ETC
M12
VSS
VSS—ETC
M9
VSS
VSS—ETC
Pin Information (continued)
Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
Pin
2C/2T06A Pad
2C/2T08A Pad
2C/2T10A Pad
2C/2T12A Pad
2C/2T15A/B Pad
Function
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.