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| 型號： | OR2C06A-2M256I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CAP 0.01UF 100V 10% NP0(C0G) SMD-1805 T&R SOLDER-COATED P-MIL-PRF-55681 |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 156/192頁 |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2C06A-2M256I |
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Data Sheet
ORCA Series 2 FPGAs
June 1999
66
Lucent Technologies Inc.
Pin Information
Pin Descriptions
This section describes the pins found on the Series 2 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
Table 17. Pin Descriptions
Symbol
I/O
Description
Dedicated Pins
VDD
—
Positive power supply.
GND
—
Ground supply.
I/O-VDD5
—
5 V tolerant select. (For 2TxxA only.) All VDD5 pins must be tied to either the 5 V power
supply if 5 V tolerant I/O buffers are to be used, or to the 3.3 V power supply (VDD) if
they are not. For 2CxxA and 2TxxB devices, these pins are user-programmable I/Os.
RESET
I
During configuration, RESET forces the restart of configuration and a pull-up is
enabled. After configuration, RESET can be used as a general FPGA input or as a
direct input, which causes all PLC latches/FFs to be asynchronously set/reset.
CCLK
I
In the master and asynchronous peripheral modes, CCLK is an output which strobes
configuration data in. In the slave or synchronous peripheral mode, CCLK is input syn-
chronous with the data on DIN or D[7:0].
DONE
I/O
DONE is a bidirectional pin with an optional pull-up resistor. As an active-high, open-
drain output, a high-level on this signal indicates that configuration is complete. As an
input, a low level on DONE delays FPGA start-up after configuration*.
PRGM
IPRGM is an active-low input that forces the restart of configuration and resets the
boundary-scan circuitry. This pin always has an active pull-up.
RD_CFG
I
This pin must be held high during device initialization until the INIT pin goes high.
This pin always has an active pullup.
During configuration, RD_CFG is an active-low input that activates the TS_ALL function
and 3-states all of the I/O.
After configuration, RD_CFG can be selected (via a bit stream option) to activate the
TS_ALL function as described above, or, if readback is enabled via a bit stream option,
a high-to-low transition on RD_CFG will initiate readback of the configuration data,
including PFU output states, starting with frame address 0.
RD_DATA/TDO
O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configu-
ration data out. If used in boundary scan, TDO is test data out.
Special-Purpose Pins (Become User I/O After Configuration)
RDY/RCLK
O
During configuration in peripheral mode, RDY indicates another byte can be written to
the FPGA. If a read operation is done when the device is selected, the same status is
also available on D7 in asynchronous peripheral mode. After configuration, the pin is a
user-programmable I/O*.
During the master parallel configuration mode RCLK, which is a read output signal to an
external memory. This output is not normally used. After configuration, this pin is a user-
programmable I/O pin*.
DIN
I
During slave serial or master serial configuration modes, DIN accepts serial configura-
tion data synchronous with CCLK. During parallel configuration modes, DIN is the D0
input. During configuration, a pull-up is enabled, and after configuration, this pin is a
user-programmable I/O pin*.
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the acti-
vation of all user I/Os) is controlled by a second set of options.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2C06A-2M84 | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R (BX); Lead Style: Surface Mount Chip; Lead Dimensions: 1805; Termination: Solder Coated SnPb; Body Dimensions: 0.180" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: R Failure Rate |
| OR2C06A-2M84I | Field-Programmable Gate Arrays |
| OR2C06A-2PS208 | Field-Programmable Gate Arrays |
| OR2C06A-2PS208I | Field-Programmable Gate Arrays |
| OR2C06A-2PS240 | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C06A-2M84 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A-2M84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A-2PS100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A-2PS100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A-2PS144 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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