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參數(shù)資料
| 型號： | OR2C04A-7BA160 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 55/192頁 |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2C04A-7BA160 |
Data Sheet
ORCA Series 2 FPGAs
June 1999
148
Lucent Technologies Inc.
Timing Characteristics (continued)
Note: Speed grades of -5, -6, and -7 are for OR2TxxA devices only.
Table 41A. OR2CxxA and OR2TxxA PFU Output MUX, PLC BIDI, and Direct Routing Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C
≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C
≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
Symbol
Speed
Unit
-2
-3
-4
-5
-6
-7
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
PFU Output MUX (TJ = 85 °C, VDD = min)
Output MUX Delay (F[3:0]/Q[3:0] to O[4:0]) OMUX_DEL
—
1.1
—
0.8
—
0.6
—
0.5
—
0.4
—
0.4
ns
PLC 3-Statable BIDIs (TJ = 85 °C, VDD = min)
BIDI Propagation Delay
BIDI 3-state Enable/Disable Delay
TRI_DEL
TRIEN_DEL
—
1.2
1.7
—
1.0
1.3
—
0.8
1.0
—
0.7
0.8
—
0.6
0.8
—
0.5
0.7
ns
Direct Routing (TJ = 85 °C, VDD = min)
PFU to PFU Delay (xSW)
PFU Feedback (xSW)
DIR_DEL
FDBK_DEL
—
1.4
1.0
—
1.1
0.8
—
0.9
0.7
—
0.7
0.6
—
0.6
0.5
—
0.6
0.5
ns
Table 41B. OR2TxxB PFU Output MUX, PLC BIDI, and Direct Routing Timing Characteristics
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C
≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Parameter
Symbol
Speed
Unit
-7
-8
Min
Max
Min
Max
PFU Output MUX (TJ = 85 °C, VDD = min)
Output MUX Delay (F[3:0]/Q[3:0] to O[4:0])
OMUX_DEL
—
0.4
—
0.4
ns
PLC 3-Statable BIDIs (TJ = 85 °C, VDD = min)
BIDI Propagation Delay
BIDI 3-state Enable/Disable Delay
TRI_DEL
TRIEN_DEL
—
0.7
1.1
—
0.6
0.9
ns
Direct Routing (TJ = 85 °C, VDD = min)
PFU to PFU Delay (xSW)
PFU Feedback (xSW)
DIR_DEL
FDBK_DEL
—
0.6
0.4
—
0.5
0.4
ns
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| OR2C04A-7BA84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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