參數(shù)資料
型號: OP496
廠商: Analog Devices, Inc.
英文描述: Micropower, Rail-to-Rail Input and Output Operational Amplifiers(微功耗,滿幅度輸入輸出四運放)
中文描述: 微功耗,軌到軌輸入和輸出運算放大器(微功耗,滿幅度輸入輸出四運放)
文件頁數(shù): 4/16頁
文件大?。?/td> 242K
代理商: OP496
OP196/OP296/OP496
ELECTRICAL SPECIFICATIONS
REV. A
–4–
Parameter
Symbol
Conditions
Min
T yp
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
V
OS
OP196G, OP296G, OP496G
0
°
C
T
A
+125
°
C
OP296H, OP496H
0
°
T
A
+125
°
C
–40
°
C
T
A
+125
°
C
35
300
650
800
1.2
±
35
±
5
±
15
+12
μ
V
μ
V
μ
V
mV
nA
nA
nA
V
Input Bias Current
Input Offset Current
I
B
I
OS
±
10
±
1
–40
°
C
T
A
+125
°
C
Input Voltage Range
Common-Mode Rejection Ratio
V
CM
CMRR
0
0 V
V
CM
+12 V,
–40
°
C
T
A
+125
°
C
R
L
= 100 k
G Grade, Note 1
H Grade, Note 1
G Grade, Note 2
H Grade, Note 2
65
300
dB
V/mV
μ
V
mV
μ
V/
°
C
μ
V/
°
C
Large Signal Voltage Gain
Long-T erm Offset Voltage
A
VO
V
OS
1000
550
1
Offset Voltage Drift
V
OS
/
T
1.5
2
OUT PUT CHARACT ERIST ICS
Output Voltage Swing High
V
OH
I
L
= 100
μ
A
I
L
= 1 mA
I
L
= –100
μ
A
I
L
= –1 mA
11.85
11.30
V
V
mV
mV
mA
Output Voltage Swing Low
V
OL
70
450
Output Current
I
OUT
±
4
POWER SUPPLY
Supply Current per Amplifier
I
SY
V
OUT
= 6 V, R
L
=
–40
°
C
T
A
+125
°
C
60
80
+12
μ
A
μ
A
V
Supply Voltage Range
V
S
+3
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
m
R
L
=100 k
0.3
450
50
V/
μ
s
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
e
n
p-p
e
n
i
n
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.8
26
0.19
μ
V p-p
nV/
Hz
pA/
Hz
NOT ES
1
Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125
°
C, with an LT PD of 1.3.
2
Offset voltage drift is the average of the –40
°
C to +25
°
C delta and the +25
°
C to +125
°
C delta.
Specifications subject to change without notice.
WAFER TEST LIMTS
(@ V
S
= +5.0 V, V
CM
= +2.5 V, T
A
= +25
8
C unless otherwse noted)
Parameter
Symbol
Conditions
Limit
Units
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
1
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing High
Output Voltage Swing Low
Supply Current per Amplifier
V
OS
I
B
I
OS
V
CM
CMRR
PSRR
A
VO
V
OH
V
OL
I
SY
300
±
35
±
5
0 to +5
60
80
100
4.85
70
60
μ
V max
nA max
nA max
V min
dB min
dB min
V/mV min
V min
mV max
μ
A max
0 V
V
CM
5 V
±
1.5 V
V
S
±
6 V
R
L
= 100 k
I
L
= 100
μ
A
I
L
= –100
μ
A
V
OUT
= 2.5 V, R
L
=
NOT ES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1
Guaranteed by CMRR test.
(@ V
S
= +12.0 V, V
CM
= +6 V, T
A
= +25
8
C unless otherwse noted)
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