參數(shù)資料
型號: op495
廠商: Analog Devices, Inc.
英文描述: Rail to Rail Quad OP AMP(滿幅度四運算放大器)
中文描述: 軌至軌四路運算放大器(滿幅度四運算放大器)
文件頁數(shù): 3/12頁
文件大?。?/td> 337K
代理商: OP495
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
T yp
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
V
OS
30
300
800
20
30
±
3
±
5
+13.5
μ
V
μ
V
nA
nA
nA
nA
V
dB
V/mV
μ
V/
°
C
–40
°
C
T
A
+125
°
C
V
CM
= 0 V
V
CM
= 0 V, –40
°
C
T
A
+125
°
C
V
CM
= 0 V
V
CM
= 0 V, –40
°
C
T
A
+125
°
C
Input Bias Current
I
B
7
Input Offset Current
I
OS
±
1
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
Offset Voltage Drift
OUT PUT CHARACT ERIST ICS
Output Voltage Swing High
V
CM
CMRR
A
VO
V
OS
/
T
–15
90
1000
–15.0 V
V
CM
+13.5 V, –40
°
C
T
A
+125
°
C
R
L
= 10 k
110
4000
1
V
OH
R
L
= 100 k
to GND
R
L
= 10 k
to GND
R
L
= 100 k
to GND
R
L
= 10 k
to GND
14.95
14.80
V
V
V
V
mA
Output Voltage Swing Low
V
OL
–14.95
–14.85
Output Current
I
OUT
±
15
±
25
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
=
±
1.5 V to
±
15 V
V
S
=
±
1.5 V to
±
15 V, –40
°
C
T
A
+125
°
C
V
O
= 0 V, R
L
=
, V
S
=
±
18 V,
–40
°
C
T
A
+125
°
C
90
85
110
dB
dB
Supply Current
I
SY
175
+36 (
±
18)
μ
A
V
Supply Voltage Range
V
S
+3 (
±
1.5)
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
θ
O
R
L
= 10 k
0.03
85
83
V/
μ
s
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
e
n p-p
e
n
i
n
0.1 Hz to 10 Hz
f =1 kHz
f = 1 kHz
1.25
45
<0.1
μ
V p-p
nV/
Hz
pA/
Hz
Specifications subject to change without notice.
WAFER TEST LIMTS
Parameter
Symbol
Conditions
Limit
Units
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
1
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing High
Supply Current Per Amplifier
Vos
I
B
I
OS
V
CM
CMRR
PSRR
A
VO
V
OH
I
SY
300
20
±
2
0 to +4
90
90
1000
4.9
150
μ
V max
nA max
nA max
V min
dB min
μ
V/V
V/mV min
V min
μ
A max
0 V
V
CM
4 V
±
1.5 V
V
S
±
15 V
R
L
= 10 k
R
L
= 10 k
V
OUT
= 2.5 V, R
L
=
NOT ES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1
Guaranteed by CMRR test.
ORDE RING GUIDE
OP295/OP495
REV. B
–3–
(@ V
S
=
±
15.0 V, T
A
= +25
8
C unless otherwse noted)
T emperature
Range
Package
Description
Package
Option
Model
OP295GP
OP295GS
OP295GBC
–40
°
C to +125
°
C
–40
°
C to +125
°
C
+25
°
C
8-Pin Plastic DIP
8-Pin SOIC
DICE
N-8
SO-8
T emperature
Range
Package
Description
Package
Option
Model
OP495GP
OP495GS
OP495GBC +25
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
14-Pin Plastic DIP
16-Pin SOL
DICE
N-14
R-16
(@ V
S
= +5.0 V, V
CM
= 2.5 V, T
A
= +25
8
C unless otherwse noted)
相關PDF資料
PDF描述
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