
OP467
WAFER TEST LIMITS
1
REV. C
–4–
Parameter
Symbol
Conditions
Limit
±
0.5
600
100
±
12
80
96
83
±
13.0
10
Units
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
2
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply Current
V
OS
I
B
I
OS
mV max
nA max
nA max
V min/max
dB min
dB min
dB min
V min
mA max
V
CM
= 0 V
V
CM
= 0 V
CMRR
PSRR
A
VO
V
O
I
SY
V
CM
=
±
12 V
V =
±
4.5 V to
±
18 V
R
L
= 2 k
R
L
= 2 k
V
O
= 0 V, R
L
=
∞
NOTES
1
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
2
Guaranteed by CMR test.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Differential Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . .
±
26 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . .Limited
Storage Temperature Range
Y, RC Packages . . . . . . . . . . . . . . . . . . . . –65
°
C to +175
°
C
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Operating Temperature Range
OP467A . . . . . . . . . . . . . . . . . . . . . . . . . . –55
°
C to +125
°
C
OP467G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
Junction Temperature Range
Y, RC Packages . . . . . . . . . . . . . . . . . . . . –65
°
C to +175
°
C
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature Range (Soldering, 60 sec) . . . . . . .+300
°
C
Package Type
u
A3
94
76
88
78
u
JC
10
33
23
33
Units
°
C/W
°
C/W
°
C/W
°
C/W
14-Lead Cerdip (Y)
14-Lead Plastic DIP (P)
16-Lead SOL (S)
20-Contact LCC (RC)
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than
±
18 V, the absolute maximum input voltage is equal
to the supply voltage.
3
θ
JA
is specified for the worst case conditions, i.e.,
θ
JA
is specified for device in socket
for cerdip, P-DIP, and LCC packages;
θ
JA
is specified for device soldered in circuit
board for SOIC package.
ORDERING GUIDE
Temperature
Ranges
Package
Descriptions
Package
Options
Model
OP467AY/883
OP467ARC/883 –55
°
C to +125
°
C 20-Contact LCC
OP467GP
–40
°
C to +85
°
C
OP467GS
–40
°
C to +85
°
C
OP467GBC
+25
°
C
–55
°
C to +125
°
C 14-Lead Cerdip
Q-14
E-20A
14-Lead Plastic DIP N-14
16-Lead SOL
DICE
R-16
DICE CHARACTERISTICS
OP467 Die Size 0.111
3
0.100 inch, 11,100 sq. mils Sub-
strate is Connected to V+, Number of Transistors 165.
(
@ V
S
=
6
15.0 V, T
A
= +25
8
C unless otherwise noted.)