
OP279
Typical Performance Graphs
–6–
REV. D
T HE ORY OF OPE RAT ION
T he OP279 is the latest entry in Analog Devices’ expanding
family of single-supply devices, designed for the multimedia and
telecom marketplaces. It is a high output current drive, rail-to-
rail input /output operational amplifier, powered from a single
+5 V supply. It is also intended for other low supply voltage
applications where low distortion and high output current drive
are needed. T o combine the attributes of high output current
and low distortion in rail-to-rail input/output operation, novel
circuit design techniques are used.
For example, Figure 1 illustrates a simplified equivalent circuit
for the OP279’s input stage. It is comprised of two PNP differ-
ential pairs, Q5-Q6 and Q7-Q8, operating in parallel, with
diode protection networks. Diode networks D5-D6 and D7-D8
serve to clamp the applied differential input voltage to the
OP279, thereby protecting the input transistors against ava-
lanche damage. T he fundamental differences between these
two PNP gain stages are that the Q7-Q8 pair are normally OFF
and that their inputs are buffered from the operational amplifier
inputs by Q1-D1-D2 and Q9-D3-D4. Operation is best under-
stood as a function of the applied common-mode voltage:
When the inputs of the OP279 are biased midway between the
supplies, the differential signal path gain is controlled by the
resistively loaded (via R7, R8) Q5-Q6. As the input common-
mode level is reduced toward the negative supply (V
NEG
or
GND), the input transistor current sources, I1 and I3, are
forced into saturation, thereby forcing the Q1-D1-D2 and
Q9-D3-D4 networks into cutoff; however, Q5-Q6 remain
active, providing input stage gain. On the other hand, when the
common-mode input voltage is increased toward the positive
supply, Q5-Q6 are driven into cutoff, Q3 is driven into satura-
tion, and Q4 becomes active, providing bias to the Q7-Q8 dif-
ferential pair. T he point at which the Q7-Q8 differential pair
becomes active is approximately equal to (V
POS
– 1 V).
I2
R5
4k
V
D7
I1
R6
4k
V
D8
D5
D6
R3
2.5k
V
R4
2.5k
V
Q4
Q3
Q2
Q5
Q6
Q9
Q1
R1
6k
V
R2
3k
V
V
POS
V
NEG
R7
2.2k
V
R8
2.2k
V
I3
D1
D2
D3
D4
V
O
–
+
IN–
IN+
Q8
Q7
Figure 22. OP279 Equivalent Input Circuit
T he key issue here is the behavior of the input bias currents in
this stage. T he input bias currents of the OP279 over the range
of common-mode voltages from (V
NEG
+ 1 V) to (V
POS
– 1 V)
are the arithmetic sum of the base currents in Q1-Q5 and Q9-
Q6. Outside of this range, the input bias currents are domi-
nated by the base current sum of Q5-Q6 for input signals close
to V
NEG
, and of Q1-Q5 (Q9-Q6) for input signals close to V
POS
.
As a result of this design approach, the input bias currents in
the OP279 not only exhibit different amplitudes, but also ex-
hibit different polarities. T his input bias current behavior is
best illustrated in Figure 3. It is, therefore, of paramount im-
portance that the effective source impedances connected to
the OP279’s inputs are balanced for optimum dc and ac
performance.
100
60
0
10
10k
1k
100
1
40
20
80
FREQUENCY – Hz
V
!
H
V
S
= +5V
T
A
= +25
8
C
Figure 19. Voltage Noise Density vs.
Frequency
120
60
0
1k
1M
100k
10k
100
40
20
80
100
FREQUENCY – Hz
C
T
A
= +25
8
C
V
S
6
2.5V
Figure 21. Common-Mode
Rejection vs. Frequency
COMMON-MODE VOLTAGE – Volts
60
0
5
30
10
1
20
0
50
40
4
3
2
V
!
H
V
S
= +5V
T
= +25
8
C
FREQUENCY = 1kHz
Figure 20. Voltage Noise Density vs.
Common-Mode Voltage