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參數(shù)資料
| 型號(hào)： | OP249AZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP JFET 4.7MHZ DUAL 8CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 22 V/µs |
| 增益帶寬積： | 4.7MHz |
| 電流 - 輸入偏壓： | 30pA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 5.6mA |
| 電流 - 輸出 / 通道： | 36mA |
| 電壓 - 電源，單路/雙路(±)： | ±4.5 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-CERDIP |
| 包裝： | 管件 |
OP249
Data Sheet
Rev. H | Page 16 of 20
10
0%
100
90
500mV
1s
4s
10
0%
100
90
500mV
1s
4s
A
C = 5pF
RESPONSE IS GROSSLY UNDERDAMPED,
AND EXHIBITS RINGING
B
C = 15pF
FAST RISE TIME CHARACTERISTICS, BUT AT EXPENSE
OF SLIGHT PEAKING IN RESPONSE
00296-
049
Figure 49. Effect of Altering Compensation from Circuit in Figure 47—PM7545 CMOS DAC with 1/2 OP249, Unipolar Operation;
Critically Damped Response Is Obtained with C ≈ 33 pF
Figure 49 illustrates the effect of altering the compensation on
the output response of the circuit in Figure 47. Compensation is
required to address the combined effect of the output capacitance
of the DAC, the input capacitance of the op amp, and any stray
capacitance. Slight adjustments to the compensation capacitor may
be required to optimize settling response for any given application.
The settling time of the combination of the current output DAC
and the op amp can be approximated by
(
) (
)2
2
AMP
t
DAC
t
TOTAL
t
S
+
=
The actual overall settling time is affected by the noise gain of
the amplifier, the applied compensation, and the equivalent
input capacitance at the input of the amplifier.
DISCUSSION ON DRIVING ADCs
Settling characteristics of op amps also include the ability of the
amplifier to recover, that is, settle, from a transient current output
load condition. An example of this includes an op amp driving
the input from a SAR-type ADC. Although the comparison
point of the converter is usually diode clamped, the input swing
of plus-and-minus a diode drop still gives rise to a significant
modulation of input current. If the closed-loop output impedance
is low enough and bandwidth of the amplifier is sufficiently
large, the output settles before the converter makes a comparison
decision, which prevents linearity errors or missing codes.
Figure 50 shows a settling measurement circuit for evaluating
recovery from an output current transient. An output disturbing
current generator provides the transient change in output load
current of 1 mA.
+15V
1.5k
1N4148
220
1.8k
2N3904
1k
*
TTL INPUT
+15V
2N2907
7A13 PLUG-IN
300pF
1/2
OP249
+
1k
|VREF|
ΔIOUT =
–15V
0.1F
10F
VREF
0.01F
1k
0.47F
3
2
8
1
4
*DECOUPLE CLOSE TOGETHER ON GROUND
PLANE WITH SHORT LEAD LENGTHS.
00296-
050
Figure 50. Transient Output Impedance Test Fixture
As seen in Figure 51, the OP249 has an extremely fast recovery
of 247 ns (to 0.01%) for a 1 mA load transient. The performance
makes it an ideal amplifier for data acquisition systems.
10
0%
100
90
100ns
2V
2mV
247.4ns
00296-
051
Figure 51. Transient Recovery Time of the OP249 from
a 1 mA Load Transient to 0.01%
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OP249AZ/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:OP-AMP|DUAL|BIPOLAR/JFET|DIP|8PIN|CERAMIC |
| OP249AZMDA | 制造商:Analog Devices 功能描述: |
| OP249EJ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual, Precision JFET High Speed Operational Amplifier |
| OP249EZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| OP249FJ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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