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參數(shù)資料
| 型號(hào)： | OP1177ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/24頁(yè) |
| 文件大小： | 0K |
| 描述： | IC OPAMP GP 1.3MHZ PREC LN 8SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Power Line Monitoring Top Five Instrumentation Amplifier Problems |
| 設(shè)計(jì)資源： | Versatile High Precision Programmable Current Sources Using DACs, Op Amps, and MOSFET Transistors (CN0151) How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 0.7 V/µs |
| 增益帶寬積： | 1.3MHz |
| 電流 - 輸入偏壓： | 500pA |
| 電壓 - 輸入偏移： | 15µV |
| 電流 - 電源： | 400µA |
| 電流 - 輸出 / 通道： | 10mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 36 V，±2.5 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | OP1177ARZ-REEL7DKR |
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OP1177/OP2177/OP4177
Rev. G | Page 17 of 24
OP1177
6
7
2
3
4
V+
V–
VOUT
RS
+
–
400mV
CS
CL
0
26
27
-05
8
Figure 58. Snubber Network Configuration
Caution: The snubber technique cannot recover the loss of
bandwidth induced by large capacitive loads.
STRAY INPUT CAPACITANCE COMPENSATION
The effective input capacitance in an operational amplifier
circuit (Ct) consists of three components. These are the internal
differential capacitance between the input terminals, the internal
common-mode capacitance of each input to ground, and the
external capacitance including parasitic capacitance. In the
circuit in Figure 59, the closed-loop gain increases as the signal
frequency increases.
The transfer function of the circuit is
()
R1
sC
R1
R2
t
+
1
indicating a zero at
()
t
C
R2
R1
R2R1C
R1
R2
s
/
2
1
π
=
+
=
Depending on the value of R1 and R2, the cutoff frequency of
the closed-loop gain can be well below the crossover frequency.
In this case, the phase margin (ΦM) can be severely degraded,
resulting in excessive ringing or even oscillation.
A simple way to overcome this problem is to insert a capacitor
in the feedback path, as shown in Figure 60.
The resulting pole can be positioned to adjust the phase margin.
Setting Cf = (R1/R2) Ct achieves a phase margin of 90°.
R2
R1
V1
+
–
OP1177
2
3
VOUT
Ct
02
62
7-
0
59
6
7
4
V+
V–
Figure 59. Stray Input Capacitance
R2
R1
V1
+
–
OP1177
2
3
VOUT
Ct
Cf
02
62
7-
0
60
6
7
4
V+
V–
Figure 60. Compensation Using Feedback Capacitor
REDUCING ELECTROMAGNETIC INTERFERENCE
A number of methods can be utilized to reduce the effects of
EMI on amplifier circuits.
In one method, stray signals on either input are coupled to the
opposite input of the amplifier. The result is that the signal is
rejected according to the CMRR of the amplifier.
This is usually achieved by inserting a capacitor between the inputs
of the amplifier, as shown in Figure 61. However, this method can
also cause instability, depending on the value of capacitance.
R2
R1
V1
+
–
OP1177
2
3
VOUT
C
02
627
-06
1
6
7
4
V+
V–
Figure 61. EMI Reduction
Placing a resistor in series with the capacitor (see Figure 62)
increases the dc loop gain and reduces the output error. Positioning
the breakpoint (introduced by R-C) below the secondary pole of
the operational amplifier improves the phase margin and,
therefore, stability.
R can be chosen independently of C for a specific phase margin
according to the formula
()
+
=
R1
R2
jf
a
R2
R
2
1
where:
a is the open-loop gain of the amplifier.
f2 is the frequency at which the phase of a = ΦM 180°.
OP1177
2
3
R
C
R1
R2
VOUT
V1
+
–
02
62
7-
06
2
6
7
4
V+
V–
Figure 62. Compensation Using Input R-C Network
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