
OP113/OP213/OP413
WAFER TEST LIMTS
–4–
REV. B
Parameter
Symbol
Conditions
Limit
Units
Offset Voltage
V
OS
V
S
=
±
15 V
V
CM
= 0, V
OUT
= 2 V
V
CM
= 0 V
V
CM
= 0 V
±
100
±
150
650
50
0 to 4
90
100
2
4.0
2.0
μ
V max
μ
V max
nA max
nA max
V min
dB min
μ
V/V
V/
μ
V min
V min
mA max/amp
Input Bias Current
Input Offset Current
Input Voltage Range
1
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing High
Supply Current/Amplifier
I
B
I
OS
CMRR
PSRR
A
VO
V
OH
I
SY
0
≤
V
CM
≤
4 V
V
S
=
±
2 V to
±
18 V
R
L
= 2 k
, V
S
=
±
15 V
R
L
= 600
V
O
= 0 V, R
L
=
∞
, V
S
, V
S
=
±
18 V
NOT ES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1
Guaranteed by CMR test.
(@ V
S
= +5.0 V, T
A
= +25
8
C unless otherwse noted)
ABSOLUT E MAX IMUM RAT INGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .
±
10 V
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage T emperature Range
Z, Y Package . . . . . . . . . . . . . . . . . . . . . . . –65
°
C to +175
°
C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Operating T emperature Range
OP113/OP213/OP413A, B . . . . . . . . . . . . . –55
°
C to +125
°
C
OP113/OP213/OP413E, F . . . . . . . . . . . . . . –40
°
C to +85
°
C
Junction T emperature Range
Z, Y Package . . . . . . . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead T emperature Range (Soldering, 60 sec) . . . . . . . +300
°
C
Package T ype
u
JA
u
JC
Units
8-Pin Cerdip (Z)
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
14-Pin Cerdip (Y)
14-Pin Plastic DIP (P)
16-Pin SOL (S)
148
103
158
108
83
92
16
43
43
16
39
27
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
NOT ES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
θ
is specified for the worst case conditions, i.e.,
θ
is specified for device in socket
for cerdip, P-DIP, and LCC packages;
θ
JA
is specified for device soldered in circuit
board for SOIC package.
DICE CHARACT E RIST ICS
OP113 Die Size 0.064 X 0.0627 inch, 3,968 sq. mils.
Substrate (Die Backside) Is Connected to V+.
Transistor Count, 66.
ORDE RING GUIDE
T emperature
Range
Package
Description
Package
Option
Model
OP113EP
OP113ES
OP113FP
OP113FS
OP213EP
OP213ES
OP213FP
OP213FS
OP413EP
OP413ES
OP413FP
OP413FS
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
8-Pin Plastic DIP
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
14-Pin Plastic DIP N-14
16-Pin SOL
14-Pin Plastic DIP N-14
16-Pin SOL
N-8
SO-8
N-8
SO-8
N-8
SO-8
N-8
SO-8
SOL-16
SOL-16