
I-Cube, Inc.
[Rev. 1.6] 2/20/01
5
OCX160 Crosspoint Switch
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Preliminary Data Sheet
Figures
Figure 1
OCX160 Functional Block Diagram .................................................................................................... 1
Figure 2
OCX160 Switch Matrix........................................................................................................................ 7
Figure 3
Input and Output Buffer Configuration................................................................................................ 8
Figure 4
Next Neighbor Clock Block Diagram ................................................................................................10
Figure 5
OCX160 JTAG Architecture.............................................................................................................. 15
Figure 6
OCX160 JTAG State Machine........................................................................................................... 16
Figure 7
Transmitting LVDS Signal Circuit..................................................................................................... 22
Figure 8
Receiving LVDS Signal Circuit ......................................................................................................... 22
Figure 9
Transmitting LVPECL Signal Circuit ................................................................................................23
Figure 10
Receiving LVPECL Signal Circuit..................................................................................................... 23
Figure 11
Registered Output Mode Timing........................................................................................................ 28
Figure 12
Flow-Through Mode Timing.............................................................................................................. 28
Figure 13
Output Enable Timing ........................................................................................................................ 28
Figure 14
Duty Cycle Distortion......................................................................................................................... 29
Figure 15
RapidConfigure Write Cycle.............................................................................................................. 29
Figure 16
RapidConfigure Read Cycle............................................................................................................... 30
Figure 17
JTAG Timing......................................................................................................................................30
Figure 18
Typical Performance LVDS mode ..................................................................................................... 31
Figure 19
Typical Performance LVPECL mode................................................................................................. 31
Figure 20
OCX160 Package Pinout.................................................................................................................... 32
Figure 21
OCX160 Package
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Bottom, Top and Side Views............................................................................. 38
Figure 22
Power Consumption Diagram for the OCX160 using LVDS............................................................. 40
Figure 23
Power Consumption Diagram for the OCX160 using LVPECL........................................................ 41