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參數(shù)資料
| 型號： | NT5SE8M16DS-6K |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 3/64頁 |
| 文件大?。?/td> | 1153K |
| 代理商： | NT5SE8M16DS-6K |
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NT5SV8M16DS / NT5SV8M16DT
NT5SE8M16DS / NT5SE8M16DT
128Mb Synchronous DRAM
REV 1.0
May 9, 2005
11
NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock.
The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or
interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears
on the outputs is equal to the value of the CAS latency that is set in the Mode Register.
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that
the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remain-
ing addresses are overridden by the new address with the burst length. The data from the first Read Command continues to
appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the
interrupting Read Command appears.
Burst Read Operation
Read Interrupted by a Read
COMMAND
READ A
NOP
DOUT A0
CAS latency = 2
tCK3, DQs
CAS latency = 3
DOUT A1
DOUT A2
DOUT A3
NOP
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
tCK2, DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
(Burst Length = 4, CAS latency = 2, 3)
COMMAND
READ A
READ B
NOP
tCK2, DQs
CAS latency = 2
tCK3, DQs
CAS latency = 3
NOP
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
(Burst Length = 4, CAS latency = 2, 3)
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