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參數(shù)資料
| 型號： | NM95MS14 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Plug n Play Front-End Devices for ISA-Bus Systems |
| 中文描述： | 插銷N播放前端ISA設(shè)備，總線系統(tǒng) |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 162K |
| 代理商： | NM95MS14 |
Chipselect Generation
Individual I/O chipselect can be generated in the following
two ways:
A) Address Decode only
B) Address Decode qualified by Command (IORD
*
, IOWR
*
).
On-Chip EEPROM
NM95MS14 has 6k of EEPROM on chip. All the PnP re-
source data structure for the logical device is stored in this
EEPROM. Of the 6k bits, 4k bits are available for the logical
device’s external usage. The logical device can access the
EEPROM through a microwire port, which is essentially a
4-wire serial bus. The pins CS, SK, DI & DO follow the exact
timing as the standard microwire bus and are compatible to
the NM93Cxx family of EEPROMs.
EEPROM Programming
The entire 6k bits of EEPROM can be programmed through
the ISA bus. The EEPROM can be programmed by putting
the device (NM95MS14) in the Config. state (as defined in
the PnP standard). Under this state 4 registers at address
0xF0–0xF3 are accessible to program the EEPROM. The
data to be programmed is loaded in register at address
0xF3 and 0xF2 (LSB and MSB respectively). The address to
be programmed is loaded in register at address 0xF1. The
Ninth bit of address for 6k bits of memory is provided
through the register at address 0xF0. Both read write are
possible. The actual operation does not begin until Go
Ahead (GA) bit is set. Programming a word takes approxi-
mately 10 ms. The status of the operation can be polled by
the Status bit. This bit is set when the operation is in prog-
ress and will be reset when complete. The register at ad-
dress 0xF0 is COMMAND register. This is the handshake
register in programming the EEPROM and is explained be-
low in a tabular format.
COMMAND register
0xF0
Bit
[
1:0
]
- OP Code bits
10 - Read operation
01 - Write operation
Bit
[
2
]
GA(Go ahead bits)
If set to 1 the programming will continue.
Bit
[
6:3
]
Bit
[
7
]
- Reserved, should be 0.
- It provides A8 of the address. A
[
0:7
]
is provided by 0xF1 reg. (Note 1)
Address Register
0xF1
AddressRegister
[
A0–A7
]
Data Register
0xF2
Data Byte
[
MSB
]
Data Register
0xF3
Data Byte
[
LSB
]
STATUS Register
0x05
Bit
[
0
]
- Status/Busy bit
‘‘0’’ is busy, ‘‘1’’ is done.
Note 1:
The PNP resource data portion of the internal memory is at high address. Hence to program that portion, Bit
[
7
]
of register 0XF0 (Address A8) should be
set to ‘‘1’’.
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