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參數(shù)資料
| 型號： | NM93C46TLZEN |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | PROM |
| 英文描述： | Microwire Serial EEPROM |
| 中文描述： | 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 204K |
| 代理商： | NM93C46TLZEN |
Functional Description
The NM93C06/C46/C56/C66LZ devices have 7 instruc-
tions as described below. Note that the MSB of any instruc-
tion is a ‘‘1’’ and is viewed as a start bit in the interface
sequence. For the C06LZ and C46LZ the next 8 bits carry
the op code and the 6-bit address for register selection. For
the C56LZ and C66LZ the next 10 bits carry the op code
and the 8-bit address for register selection.
Read (READ):
The READ instruction outputs serial data on
the DO pin. After the READ instruction is received, the in-
struction and address are decoded, followed by data trans-
fer from the selected memory register into a serial-out shift
register. A dummy bit (logical 0) precedes the 16-bit data
output string. Output data changes are initiated by a low to
high transition of the SK clock.
Erase/Write Enable (EWEN):
When V
CC
is applied to the
part, it powers up in the Erase/Write Disable (EWDS) state.
Therefore, all programming modes must be preceded by an
Erase/Write Enable (EWEN) instruction. Once an Erase/
Write Enable instruction is executed, programming remains
enabled until an Erase/Write Disable (EWDS) instruction is
executed or until V
CC
is removed from the part.
Erase (ERASE):
The ERASE instruction will program all bits
in the specified register to the logical ‘‘1’’ state. CS is
brought low following the loading of the last address bit.
This falling edge of the CS pin initiates the self-timed pro-
gramming cycle.
The DO pin indicates the READY/BUSY status of the chip.
DO
e
logical ‘‘0’’ indicates that programming is still in prog-
ress. DO
e
logical ‘‘1’’ indicates that the register, at the
address specified in the instruction, has been erased, and
the part is ready for another instruction.
Write (WRITE):
The WRITE instruction is followed by 16
bits of data to be written into the specified address. After the
last bit of data is put on the data-in (DI) pin, CS must be
brought low before the next rising edge of the SK clock.
This falling edge of CS initiates the self-timed programming
cycle. The DO pin indicates the READY/BUSY status of the
chip if CS is brought high after a minimum of 250 ns (t
CS
).
DO
e
logical 0 indicates that programming is still in prog-
ress. DO
e
1 indicates that the register at the address
specified in the instruction has been written with the data
pattern specified in the instruction and the part is ready for
another instruction.
Erase All (ERAL):
The ERAL instruction will simultaneously
program all registers in the memory array and set each bit to
the logical ‘‘1’’ state. The Erase All cycle is identical to the
ERASE cycle except for the different op code. As in the
ERASE mode, the DO pin indicates the READY/BUSY
status of the chip. The ERASE ALL instruction is not re-
quired, see note below.
Write All (WRAL):
The WRAL instruction will simultaneous-
ly program all registers with the data pattern specified in the
instruction. As in the WRITE mode, the DO pin indicates the
READY/BUSY status of the chip.
Erase/Write Disable (EWDS):
To protect against acciden-
tal data disturb, the (EWDS) instruction disables all pro-
gramming modes and should follow all programming opera-
tions. Execution of a READ instruction is independent of
both the EWEN and EWDS instructions.
Note:
The NM93C06/C46/C56/C66LZ devices do not require an ‘‘ERASE’’
or ‘‘ERASE ALL’’ prior to the ‘‘WRITE’’ or ‘‘WRITE ALL’’ instructions.
Instruction Set for the NM93C06LZ and NM93C46LZ
Instruction
SB
Op Code
Address
Data
Comments
READ
1
10
A5–A0
Read data stored in memory, at specified address
EWEN
1
00
11XXXX
Write enable must precede all programming modes
EWDS
1
11
A5–A0
Erase register A5, A4, A3, A2, A1, A0
WRITE
1
01
A5–A0
D15–D0
Writes register
ERAL
1
00
10XXXX
Erases all registers
WRAL
1
00
01XXXX
D15–D0
Writes all registers
EWDS
1
00
00XXXX
Disables all programming instructions
Instruction Set for the NM93C56LZ and NM93C66LZ
Instruction
SB
Op Code
Address
Data
Comments
READ
1
10
A7–A0
Read data stored in memory, at specified address
EWEN
1
00
11XXXXXX
Write enable must precede all programming modes
EWDS
1
11
A7–A0
Erase selected register
ERAL
1
00
10XXXXXX
Erases all registers
WRITE
1
01
A7–A0
D15–D0
Write register if address is unprotected
WRAL
1
00
01XXXXXX
D15–D0
Writes all registers
EWDS
1
00
00XXXXXX
Disables all programming instructions
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| NM93C46TLZM8 | Microwire Serial EEPROM |
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| NM93C46TLZN | Microwire Serial EEPROM |
| NM93C46TLZVM8 | Microwire Serial EEPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NM93C46TLZM8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:1024-Bit Serial CMOS EEPROM (MICROWIRE⑩ Synchronous Bus) |
| NM93C46TLZMT8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Microwire Serial EEPROM |
| NM93C46TLZN | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Microwire Serial EEPROM |
| NM93C46TLZVM8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Microwire Serial EEPROM |
| NM93C46TLZVMT8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Microwire Serial EEPROM |
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