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參數(shù)資料
| 型號： | NJU26104 |
| 廠商： | New Japan Radio Co., Ltd. |
| 英文描述： | NJU26100 Series Hardware Specification |
| 中文描述： | NJU26100系列硬件規(guī)格 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大小： | 270K |
| 代理商： | NJU26104 |
NJU26100 Series
- 14 -
Ver.2005-02-24
Table 5-2 4-Wire Serial Interface Timing Parameters
(V
DDO
=V
DDC
=V
DDR
=2.5V, V
SSO
=V
SSC
=V
SSR
=0V, Ta=25
°
C)
Parameter
Symbol
Input Data Rising Time
t
MSDr
Input Data Falling Time
t
MSDf
Serial Clock Rising Time
t
MSCr
Serial Clock Falling Time
t
MSCf
Serial Strobe Rising Time
t
MSSr
Serial Strobe Falling Time
t
MSSf
Serial Clock High Duration
t
MSCa
Serial Clock Low Duration
t
MSCn
Serial Clock Period
t
MSCc
Serial Strobe Setup Time
t
MSSs
Serial Strobe Hold Time
t
MSSh
Serial Strobe Low Duration
t
MSSa
Serial Strobe High Duration
t
MSSn
Input Data Setup Time
t
MSDis
Input Data Hold Time
t
MSDih
Output Data Delay
(From SSb)
Output Data Delay
(From SCK)
Output Data Hold Time
t
MSDoh
Output Data Turn off Time (Hi-Z)
t
MSDov
Fig. 5-1 4-Wire Serial Interface Timing
Note : *1 When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP
core at the transition of SSb=”High”.
*2 When the data-clock is more than 8 clocks, the last 8 bit data becomes valid.
*3 After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes
“High”.
*4 SDOUT is Hi-Z in case of SSb = “High”. SDOUT is CMOS output in case of SSb = “Low”.
SDOUT needs a pull-up resistor to prevent SDOUT from becoming floating level.
Timelines
a-b
a-b
d-e
f-g
p-q
m-n
e-f
g-h
e-i
n-e
j-q
n-p
q-r
b-e
e-c
Min.
-
-
-
-
-
-
50
50
250
100
30
-
40
20
20
Typ.
-
-
-
-
-
-
-
-
1.0
Max.
100
100
100
100
100
100
-
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
ns
ns
ns
t
MSDos
n-o,CL=25pF
-
-
50
ns
t
MSDo
g-k(data-6),
CL=25pF
g-k(data-7)
q-l
-
-
50
ns
0
-
-
-
-
ns
ns
40
m
n
o
SSb
p
q
r
a
c
b
7
6
5
1
0
SDIN
l
k
7
6
5
1
0
SDOUT
d
f g h
j
i
SCK
e
Hi-Z
Hi-Z
MSB
LSB
Note (3)
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