- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382358 > NGAM386SXLV-40 (Advanced Micro Devices, Inc.) High-Performance, Low-Power, Embedded Microprocessors PDF資料下載
參數(shù)資料
| 型號(hào)： | NGAM386SXLV-40 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance, Low-Power, Embedded Microprocessors |
| 中文描述： | 高性能，低功耗，嵌入式微處理器 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 582K |
| 代理商： | NGAM386SXLV-40 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
14
Am386SX/SXL/SXLV Microprocessors Data Sheet
F I N A L
SWITCHING CHARACTERISTICS
The switching characteristics given consist of output
delays, input setup requirements, and input hold re-
quirements. All switching characteristics are relative to
the CLK2 rising edge crossing the 2.0-V level.
Switching characteristic measurement is defined in
Figure 2. Inputs must be driven to the voltage levels in-
dicated by Figure 2 when switching characteristics are
measured. Output delays are specified with minimum
and maximum limits measured, as shown. The mini-
mum delay times are hold times provided to external
circuitry. Input setup and hold times are specified as
minimums, defining the smallest acceptable sampling
window. Within the sampling window, a synchronous
input signal must be stable for correct operation.
Outputs ADS, W/R, D/C, M/IO, LOCK, BHE, BLE,
A23–A1, HLDA, and SMIADS* only change at the be-
ginning of phase one. D15–D0 and SMI* write cycles
only change at the beginning of phase two. The
READY, HOLD, BUSY, ERROR, PEREQ, FLT, D15–
D0, IIBEN*, and SMIRDY* read cycles inputs are sam-
pled at the beginning of phase one. The NA, INTR,
NMI, and SMI* inputs are sampled at the beginning of
phase two.
* –
On Am386SXLV only; NC on Am386SX/SXL
Figure 2. Drive Levels and Measurement Points for Switching Characteristics
B
A
Valid
Output n
Valid
Output n+1
D
C
Valid
Input
B
A
Valid
Output n
Valid
Output n+1
D
C
Valid
Input
Max
Min
Max
Min
2 V
CLK2
(A23–A1, BHE, BLE,
ADS, M/IO, D/C,
W/R, LOCK, HLDA,
SMIADS*)
(NA, INTR, NMI, SMI*)
(READY, HOLD,
FLT, ERROR, BUSY,
PEREQ, D15–D0,
IIBEN*, SMIRDY*)
Legend: A–Maximum Output Delay Characteristic
B–Minimum Output Delay Characteristic
C–Minimum Input Setup Characteristic
D–Minimum Input Hold Characteristic
Tx
2
1
φ
φ
16305C–003
(D15–D0, SMI*)
Notes:
1. Input waveforms have tr
≤
2.0 ns from 0.8 V–2.0 V (on Am386SXLV only).
2. On Am386SX/SXL, V
T
= 1.5; on Am386SXLV, V
T
= 1.0 V for V
CC
≤
3.6 V and 1.5 V for V
CC
> 3.6 V.
3. * = On Am386SXLV only.
V
T
V
T
V
T
V
T
V
T
V
T
V
T
V
T
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NJ88C33MADP | Frequency Synthesiser (I2C BUS Programmable) |
| NJ88C33MAMP | Frequency Synthesiser (I2C BUS Programmable) |
| NJ88C33MP | Frequency Synthesiser (I2C BUS Programmable) |
| NJ88C33 | Frequency Synthesiser (I2C BUS Programmable) |
| NJ88C33MA | Frequency Synthesiser (I2C BUS Programmable) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NGAW5221S2R350GS1TRF | 制造商:NIC Components Corp 功能描述:ANTENNA MULTILAYER SMT - Tape and Reel 制造商:NIC Components Corp 功能描述:ANTENNA MULTILAYER SMT - Cut TR (SOS) |
| NGAW5221S2R510GS1TRF | 制造商:NIC Components Corp 功能描述:ANTENNA MULTILAYER SMT - Cut TR (SOS) 制造商:NIC Components Corp 功能描述:ANTENNA MULTILAYER SMT - Tape and Reel |
| NGAW5221S2R540GS1TRF | 制造商:NIC Components Corp 功能描述:ANTENNA MULTILAYER SMT - Tape and Reel 制造商:NIC Components Corp 功能描述:ANTENNA MULTILAYER SMT - Cut TR (SOS) |
| NGAW5221S2R710GS1TRF | 制造商:NIC Components Corp 功能描述:ANTENNA MULTILAYER SMT - Tape and Reel 制造商:NIC Components Corp 功能描述:ANTENNA MULTILAYER SMT - Cut TR (SOS) |
| NGAW5221S2R780GS1TRF | 制造商:NIC Components Corp 功能描述:ANTENNA MULTILAYER SMT - Tape and Reel 制造商:NIC Components Corp 功能描述:ANTENNA MULTILAYER SMT - Cut TR (SOS) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。