參數(shù)資料
型號(hào)： NG80386SX-25
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： High-Performance, Low-Power, Embedded Microprocessors
中文描述： 32-BIT, 25 MHz, MICROPROCESSOR, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 10/30頁(yè)
文件大?。?/td> 401K
代理商： NG80386SX-25
10
Am386SX/SXL/SXLV Microprocessors Data Sheet
F I N A L
PIN DESCRIPTIONS
A23–A1
Address Bus (Outputs)
Outputs physical memory or port I/O addresses.
ADS
Address Status (Active Low; Output)
Indicates that a valid bus cycle definition and address
(W/R, D/C, M/IO, BHE, BLE
, and A23–A1) are being
driven at the Am386SX/SXL/SXLV microprocessor
pins. Bus cycles initiated by ADS must be terminated
by READY.
BHE, BLE
Byte Enables (Active Low; Outputs)
Indicate which data bytes of the data bus take part in a
bus cycle.
BUSY
Busy (Active Low; Input)
Signals a busy condition from a processor extension.
BUSY has an internal pull-up resistor.
CLK2
CLK2 (Input)
Provides the fundamental timing for the Am386SX/
SXL/SXLV microprocessor.
D15–D0
Data Bus (Inputs/Outputs)
Inputs data during memory, I/O, and interrupt acknowl-
edge read cycles; outputs data during memory and I/O
write cycles.
D/C
Data/Control (Output)
A bus cycle definition pin that distinguishes data cy-
cles, either memory or I/O, from control cycles which
are interrupt acknowledge, halt, and code fetch.
ERROR
Error (Active Low; Input)
Signals an error condition from a processor extension.
ERROR has an internal pull-up resistor.
FLT
Float (Active Low; Input)
An input which forces all bidirectional and output sig-
nals, including HLDA, to the three-state condition. FLT
has an internal pull-up resistor. The pin, if not used,
should be disconnected.
HLDA
Bus Hold Acknowledge (Active High; Output)
Output indicates that the Am386SX/SXL/SXLV micro-
processor has surrendered control of its logical bus to
another bus master.
HOLD
Bus Hold Request (Active High; Input)
Input allows another bus master to request control of
the local bus.
IIBEN (Am386SXLV Only)
I/O Instruction Break Enable (Active Low; Input)
Enables the I/O instruction break feature. IIBEN has a
dynamic internal pull-up resistor. The IIBEN pull-up is
active during RESET and whenever the signal is not
driven active Low by the system.
INTR
Interrupt Request (Active High; Input)
A maskable input that signals the Am386SX/SXL/
SXLV microprocessor to suspend execution of the cur-
rent program and execute an interrupt acknowledge
function.
LOCK
Bus Lock (Active Low; Output)
A bus cycle definition pin that indicates that other sys-
tem bus masters are not to gain control of the system
bus while it is active.
M/IO
Memory/IO (Output)
A bus cycle definition pin that distinguishes memory cy-
cles from input/output cycles.
NA
Next Address (Active Low; Input)
Used to request address pipelining.
NC
No Connect
Should always be left unconnected. Connection of an
NC pin may cause the processor to malfunction or be
incompatible with future steppings of the Am386SX/
SXL/SXLV microprocessor.
NMI
Non-Maskable Interrupt Request
(Active High; Input)
A non-maskable input that signals to the Am386SX/
SXL/SXLV microprocessor to suspend execution of the
current program and execute an interrupt acknowledge
function.
PEREQ
Processor Extension Request (Active High; Input)
Indicates that the processor has data to be transferred
by the Am386SX/SXL/SXLV microprocessor. PEREQ
has an internal pull-down resistor.
相關(guān)PDF資料
PDF描述
NG80386SX-33 Diode; Antenna switching; VR (V): 30; IF (mA): 100; Pd (mW): 100; rf (ohm) max: 2.5/1.5 (HVL147M Faction) 2.0 (RKP201KN Faction); Condition IF at rf (mA): 2/10 (HVL147M Faction) 2 (RKP201KN Faction); Condition f at rf (MHz): 100; VF (V) max: 1.0 (HVL147M Faction) 0.9 (RKP201KN Faction); Condition IF at VF (mA): 10 (HVL147M Faction) 2 (RKP201KN Faction); C (pF) max: 0.31 (HVL147M Faction) 0.35 (RKP201KN Faction); Condition VR at C (V): 1; Condition f at C (MHz): 1; Package: MFP12
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NG80386SX25SX701 制造商:Intel 功能描述:32 BIT MICROPROCE
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