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參數(shù)資料
| 型號： | NE27200 |
| 廠商： | NEC Corp. |
| 英文描述： | C to Ka BAND SUPER LOW NOISE AMPLIFIER N-CHANNEL HJ-FET CHIP |
| 中文描述： | C至Ka波段超低噪聲放大器N溝道黃建忠晶體管芯片 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 39K |
| 代理商： | NE27200 |
1996
DATA SHEET
HETERO JUNCTION FIELD EFFECT TRANSISTOR
NE32500, NE27200
C to Ka BAND SUPER LOW NOISE AMPLIFIER
N-CHANNEL HJ-FET CHIP
DESCRIPTION
NE32500 and NE27200 are Hetero Junction FET chip that utilizes the hetero junction between Si-doped AlGaAs
and undoped InGaAs to create high mobility electrons. Its excellent low noise and high associated gain make it suitable
for commercial systems, industrial and space applications.
FEATURES
Super Low Noise Figure & High Associated Gain
NF = 0.45 dB TYP., G
a
= 12.5 dB TYP. at f = 12 GHz
Gate Length: L
g
= 0.2
μ
m
Gate Width : W
g
= 200
μ
m
ORDERING INFORMATION
PART NUMBER
QUALITY GRADE
NE32500
Standard (Grade D)
NE27200
Special, specific (Grade C and B)
ABSOLUTE MAXIMUM RATINGS (T
A
= 25 C)
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Total Power Dissipation
Channel Temperature
Storage Temperature
*
Chip mounted on a Alumina heatsink (size: 3
×
3
×
0.6
t
)
V
DS
V
GS
I
D
P
tot
*
T
ch
T
stg
4.0
–3.0
I
DSS
200
175
V
V
mA
mW
°
C
°
C
–65 to +175
ELECTRICAL CHARACTERISTICS (T
A
= 25 C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
Gate to Source Leak Current
I
GSO
–
0.5
10
μ
A
V
GS
= –3 V
Saturated Drain Current
I
DSS
20
60
90
mA
V
DS
= 2 V, V
GS
= 0 V
Gate to Source Cutoff Voltage
V
GS(off)
–0.2
–0.7
–2.0
V
V
DS
= 2 V, I
D
= 100
μ
A
Transconductance
g
m
45
60
–
mS
V
DS
= 2 V, I
D
= 10 mA
Thermal Resistance
R
th
*
–
–
260
C/W
channel to case
Noise Figure
NF
–
0.45
0.55
dB
V
DS
= 2 V, I
D
= 10 mA, f = 12 GHz
Associated Gain
G
a
11.0
12.5
–
dB
RF performance is determined by packaging and testing 10 chips per wafer.
Wafer rejection criteria for standard devices is 2 rejects per 10 samples.
Document No. P11512EJ2V0DS00 (2nd edition)
Date Published January 1997 N
Printed in Japan
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