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參數(shù)資料
| 型號： | NCV7341D21R2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 2/18頁 |
| 文件大小： | 0K |
| 描述： | TXRX CAN HS LOW POWER 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | CAN |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 帶卷 (TR) |
NCV7341
http://onsemi.com
10
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (Pin 2). Positive
currents flow into the IC. Sinking current means the current
is flowing into the pin; sourcing current means the current
is flowing out of the pin.
Absolute Maximum Ratings
Stresses above those listed in the following table may
cause permanent device failure. Exposure to absolute
maximum ratings for extended periods may affect device
reliability.
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min.
Max.
Unit
VBAT
Supply voltage
0.3
58
V
VCC
Supply voltage
0.3
+7
V
VIO
Supply voltage
0.3
+7
V
VCANH
DC voltage at pin CANH
0 < VCC < 5.25 V;
no time limit
58
+58
V
VCANL
DC voltage at pin CANL
0 < VCC < 5.25 V;
no time limit
58
+58
V
VCANLVCANH
DC voltage between bus pins CANH and CANL
0 < VCC < 5.25 V;
no time limit
58
+58
V
VSPLIT
DC voltage at pin VSPLIT
0 < VCC < 5.25 V;
no time limit
58
+58
V
VINH
DC voltage at pin INH
0.3
VBAT+0.3
V
VWAKE
DC voltage at pin WAKE
0.3
58
V
VTxD
DC voltage at pin TxD
0.3
7
V
VRxD
DC voltage at pin RxD
0.3
VIO + 0.3
V
VSTB
DC voltage at pin STB
0.3
7
V
VEN
DC voltage at pin EN
0.3
7
V
VERR
DC voltage at pin ERR
0.3
VIO + 0.3
V
Vtran(CANH)
Transient voltage at pin CANH
(Note 1)
300
+300
V
Vtran(CANL)
Transient voltage at pin CANL
(Note 1)
300
+300
V
Vtran(VSPLIT)
Transient voltage at pin VSPLIT
(Note 1)
300
+300
V
Vesd(CANL/CANH/
VSPLIT, VBAT, WAKE)
Electrostatic discharge voltage at pins intended to be
wired outside of the module
(CANH, CANL, VSPLIT, VBAT, WAKE)
(Note 2)
(Note 4)
4
500
4
500
kV
V
Vesd
Electrostatic discharge voltage at all other pins
(Note 2)
(Note 4)
3
500
3
500
kV
V
Latchup
Static latchup at all pins
(Note 3)
120
mA
Tstg
Storage temperature
50
+150
°C
Tamb
Ambient temperature
50
+125
°C
Tjunc
Maximum junction temperature
50
+180
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b (see Figure 9).
2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to MIL883 method 3015.7.
3. Static latch-up immunity: Static latch-up protection level when tested according to EIA/JESD78.
4. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993.
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