參數(shù)資料
型號(hào): NCV7340D14G
廠(chǎng)商: ON Semiconductor
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 0K
描述: IC TXRX CAN HS LP 8SOIC
標(biāo)準(zhǔn)包裝: 1
系列: *
NCV7340
http://onsemi.com
5
TxD Dominant Timeout Function
A TxD dominant timeout timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the lowlevel on pin TxD exceeds the
internal timer value tdom(TxD), the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant timeout time (tdom(TxD)) defines the
minimum possible bit rate to 40 kbps.
Fail Safe Features
A currentlimiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 5). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
VCC supply be removed.
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (Pin 2). Positive currents flow into the IC. Sinking current means the current is flowing
into the pin; sourcing current means the current is flowing out of the pin.
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
Supply voltage
0.3
+6
V
VCANH
DC voltage at pin CANH
0 < VCC < 5.25 V; no time limit
50
+50
V
VCANL
DC voltage at pin CANL
0 < VCC < 5.25 V; no time limit
50
+50
V
VSPLIT
DC voltage at pin VSPLIT
0 < VCC < 5.25 V; no time limit
40
+40
V
VTxD
DC voltage at pin TxD
0.3
6
V
VRxD
DC voltage at pin RxD
0.3
6
V
VSTB
DC voltage at pin STB
0.3
6
V
Vesd
Electrostatic discharge voltage at all pins
Note 1
Note 2
6
500
6
500
kV
V
Electrostatic discharge voltage at CANH and CANL pins
Note 3
12
kV
Vschaff
Transient voltage, see Figure 5
Note 5
150
100
V
Latchup
Static latchup at all pins
Note 4
120
mA
Tstg
Storage temperature
55
+150
°C
TA
Ambient temperature
40
+125
°C
TJ
Maximum junction temperature
40
+170
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIAJESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 k
W resistor.
2. Standardized charged device model ESD pulses when tested according to ESDSTM5.3.11999.
3. System human body model electrostatic discharge (ESD) pulses. Equivalent to discharging a 150 pF capacitor through a 330
W resistor.
4. Static latchup immunity: Static latchup protection level when tested according to EIA/JESD78.
5. Pulses 1, 2a, 3a and 3b according to ISO 7637 part 3. Verification by external test house.
Table 5. THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
Value
Unit
RqJA_1
Thermal Resistance JunctiontoAir, 1S0P PCB (Note 6)
Free air
125
K/W
RqJA_2
Thermal Resistance JunctiontoAir, 2S2P PCB (Note 7)
Free air
75
K/W
6. Test board according to EIA/JEDEC Standard JESD513, signal layer with 10% trace coverage.
7. Test board according to EIA/JEDEC Standard JESD517, signal layers with 10% trace coverage.
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