參數(shù)資料
型號: NCV4279A50D1R2G
廠商: ON SEMICONDUCTOR
元件分類: 固定正電壓單路輸出LDO穩(wěn)壓器
英文描述: 5 V / 150 mA LDO w/ Reset, Delay, Adjustable Reset and Early Warning
中文描述: 5 V FIXED POSITIVE LDO REGULATOR, 0.5 V DROPOUT, PDSO8
封裝: LEAD FREE, SOP-8
文件頁數(shù): 3/15頁
文件大?。?/td> 148K
代理商: NCV4279A50D1R2G
NCV4279A
http://onsemi.com
11
APPLICATION DESCRIPTION
OUTPUT REGULATOR
The output is controlled by a precision trimmed reference.
The PNP output has drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
RESET OUTPUT (RO)
A reset signal, Reset Output, RO, (low voltage) is
generated as the IC powers up. After the output voltage VQ
increases above the reset threshold voltage VRT, the delay
timer D is started. When the voltage on the delay timer VD
passes VUD, the reset signal RO goes high. A discharge of
the delay timer VD is started when VQ drops and stays below
the reset threshold voltage VRT. When the voltage of the
delay timer VD drops below the lower threshold voltage VLD
the reset output voltage VRO is brought low to reset the
processor.
The reset output RO is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
guaranteeing that RO is valid for VQ as low as 1.0 V.
RESET ADJUST (RADJ)
The reset threshold VRT can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 20. The resistor divider keeps the voltage
above the VRADJ,TH (typical 1.35 V) for the desired input
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
VRT + VRADJ, TH @ (RADJ1 ) RADJ2) RADJ2
(eq. 1)
If the reset adjust option is not needed, the RADJ pin
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
RESET DELAY (D)
The reset delay circuit provides a delay (programmable by
capacitor CD) on the reset output lead RO. The delay lead D
provides charge current ID,C (typically 6.5 mA) to the
external delay capacitor CD during the following times:
1. During Powerup (once the regulation threshold has
been exceeded).
2. After a reset event has occurred and the device is
back in regulation. The delay capacitor is set to
discharge when the regulation (VRT, reset
threshold voltage) has been violated. When the
delay capacitor discharges to VLD, the reset signal
RO pulls low.
SETTING THE DELAY TIME
The delay time is set by the delay capacitor CD and the
charge current ID. The time is measured by the delay
capacitor voltage charging from the low level of VDSAT to
the higher level VUD. The time delay follows the equation:
td + [CD (VUD * VD, SAT)] ID
(eq. 2)
Example:
Using CD = 100 nF.
Use the typical value for VD,SAT = 0.1 V.
Use the typical value for VUD = 1.8 V.
Use the typical value for Delay Charge Current ID = 6.5 mA.
td + [100 nF(1.8 * 0.1 V)] 6.5 mA + 26.2 ms (eq. 3)
Q
GND
I
RADJ
NCV4279A
CQ**
10 mF
(2.2 mF)
RO
0.1 mF
Microprocessor
D
CD
VBAT
VDD
SO
Figure 20. Application Diagram
SI
I/O
RADJ2
RADJ1
RSI1
RSI2
CI*
*CI required if regulator is located far from the power supply filter.
** CQ minimum cap required for stability is 2.2 mF while higher over/undershoots may be ex-
pected. Cap must operate at required temperature range.
RSO
RRO
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