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參數(shù)資料
| 型號(hào)： | NCP5604B |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | High Efficiency White LED Driver(高效白色LED驅(qū)動(dòng)器) |
| 中文描述： | 高效率白光LED驅(qū)動(dòng)器（高效白色發(fā)光二極管驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大?。?/td> | 359K |
| 代理商： | NCP5604B |
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NCP5604A, NCP5604B
http://onsemi.com
10
Figure 9. Using the NCP5604B to Drive a Three LED
Layout
VBAT
1
EN
IREF
AGND
PGND
2
3
4
N
5
L
6
L
7
L
8
9
C1N
VOUT
10
C1P
11
12
C2P
13
C2N
14
C
1
C
1
U1
NCP5604B
C2
220 nF/10 V
C3
220 nF/10 V
C4
4.7uF/6.3V
C5
1
GND
GND
D3
LWY87S
D2
LWY87S
D1
LWY87S
R1
100k
GND
CONTROL
Vbat
C1
220 nF/10 V
Finally, an external network can be connected across
Vout and ground, but the current through such network will
not be regulated by the NCP5604A chip (see Figure 10).
On top of that, the total current out of the Vout pin shall be
limited to 100 mA.
Figure 10. Extra Load Connected to Vout
N
12
5
6
7
8
D
L
GND
D
L
D
L
D
L
D
L
D
L
5
5
2
R
2
R
GND
C5
1 F/6.3 V
DIMMING
The dimming can be achieved by two means:
Use a digital PWM signal to control the EN pin
Use an analog signal to control the reference current
IREF pin.
The digital PWM is straightforward, yielding a zero to
100% duty cycle, but the output current is pulsed since the
system is continuously switched ON/OFF. There is no need
for extra passive component, the clock being provided by
an I/O port from the MCU (see Figure 11).
Figure 11. Basic Digital PWM Dimming Control
VBAT
C2P
C
C
L
L
L
L
1
2
3
6
R
GND
4
9
GND
PWM
EN
IREF
AGND
PGND
C2N
C3P
C3N
VOUT
Input PWM Signal Frequency:
100 Hz to 200 kHz
The PWM frequency can be up to 200 kHz once the
circuit has been properly started. On the other hand, with
a 1% to 99% span, the circuit supports a large Duty Cycle
to accommodate any range of dimming. The waveforms
given in Figure 12 illustrate the NCP5604A behavior
during the 50 kHz PWM operation. The same mechanism
applies for the NCP5604B version.
Figure 12. PWM Modulation Span: 1% to 99%
Besides the popular PWM mode, a simple analog
technique can be built with two extra components (one
resistor + one NMOS), the net advantage being a
continuous output current once the operating point has
been stabilized (see Figure 13). The absolute output
current tolerance depends upon the precision of the two
external resistors, the R
DS(on)
of the NMOS being
negligible in front of the resistor value. The example given,
Figure 13 yields a 1.0 mA output current when Q1 is OFF,
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