參數(shù)資料
型號： NCP5424DG
廠商： ON SEMICONDUCTOR
元件分類： 穩(wěn)壓器
英文描述： Dual Synchronous Buck Controller with Input Current Sharing
中文描述： 1.5 A DUAL SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PDSO16
封裝： LEAD FREE, SOIC-16
文件頁數(shù)： 13/18頁
文件大?。?/td> 148K
代理商： NCP5424DG
NCP5424
http://onsemi.com
13
PRMS(H)
IRMS(H)2
RDS(ON)
where:
P
RMS(H)
= switching MOSFET conduction losses;
I
RMS(H)
= maximum switching MOSFET RMS current;
R
DS(ON)
= FET draintosource onresistance
The upper MOSFET switching losses are caused during
MOSFET switchon and switchoff and can be determined
by using the following formula:
PSWH
PSWH(ON)
VIN
IOUT
PSWH(OFF)
(tRISE
6T
tFALL)
where:
P
SWH(ON)
= upper MOSFET switchon losses;
P
SWH(OFF)
= upper MOSFET switchoff losses;
V
IN
= input voltage;
I
OUT
= load current;
t
RISE
= MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
t
FALL
= MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
T = 1/f
SW
= period.
The total power dissipation in the switching MOSFET can
then be calculated as:
PHFET(TOTAL)
PRMS(H)
where:
P
HFET(TOTAL)
= total switching (upper) MOSFET losses;
P
RMS(H)
= upper MOSFET switch conduction Losses;
P
SWH(ON)
= upper MOSFET switchon losses;
P
SWH(OFF)
= upper MOSFET switchoff losses;
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
PSWH(ON)
PSWH(OFF)
TJ
TA
[PHFET(TOTAL)
RJA]
where:
T
J
= FET junction temperature;
T
A
= ambient temperature;
P
HFET(TOTAL)
= total switching (upper) FET losses;
R
JA
= upper FET junctiontoambient thermal resistance.
Selection of the Synchronous (Lower) FET
The switch conduction losses for the lower FET can be
calculated as follows:
IRMS2
RDS(ON)
[IOUT
(1
D)]2
RDS(ON)
PRMS(L)
where:
P
RMS(L)
= lower MOSFET conduction losses;
I
OUT
= load current;
D = Duty Cycle;
R
DS(ON)
= lower FET draintosource onresistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the nonoverlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
PSWL
VSD
ILOAD
where:
P
SWL
= lower FET switching losses;
V
SD
= lower FET sourcetodrain voltage;
I
LOAD
= load current;
Nonoverlap
time
=
GATE(H)toGATE(L) delay (from NCP5424 data sheet
Electrical Characteristics section);
f
SW
= switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
PLFET(TOTAL)
where:
P
LFET(TOTAL)
= Synchronous (lower) FET total losses;
P
RMS(L)
= Switch Conduction Losses;
P
SWL
= Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
TJ
TA
[PLFET(TOTAL)
where:
T
J
= MOSFET junction temperature;
T
A
= ambient temperature;
P
LFET(TOTAL)
= total synchronous (lower) FET losses;
R
JA
= lower FET junctiontoambient thermal resistance.
nonoverlap time
fSW
GATE(L)toGATE(H)
or
PRMS(L)
PSWL
RJA]
Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, V
CC
, and the NCP5424 operating frequency. The
average MOSFET gate charge current typically dominates
the control IC power dissipation.
The IC power dissipation is determined by the formula:
PGATE(L)1
PGATE(H)2
PGATE(L)2
PCONTROL(IC)
ICC1VCC1
IBSTVBST
PGATE(H)1
where:
P
CONTROL(IC)
= control IC power dissipation;
I
CC1
= IC quiescent supply current;
V
CC1
= IC supply voltage;
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
P
GATE(L)
= lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses
are:
PGATE(H)
QGATE(H)
where:
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
Q
GATE(H)
= total upper MOSFET gate charge at V
CC
;
f
SW
= switching frequency;
The lower (synchronous) MOSFET gate driver (IC)
losses are:
PGATE(L)
QGATE(L)
fSW
VBST
fSW
VCC
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