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參數(shù)資料
| 型號： | NCP5318 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Two/Three/Four−Phase Buck CPU Controller |
| 文件頁數(shù)： | 18/31頁 |
| 文件大?。?/td> | 384K |
| 代理商： | NCP5318 |
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NCP5318
http://onsemi.com
18
Transient Response and Adaptive Voltage Positioning
For applications with fast transient currents, the output
filter is frequently sized larger than ripple currents require in
order to reduce voltage excursions during load transients. In
addition, adaptive voltage positioning can reduce
peak
peak output voltage deviations due to load transients
and allow use of a smaller output filter. Adaptive voltage
positioning sets output voltage higher than nominal at light
loads, and output voltage is allowed limited sag when the
load current is applied. Upon removal of the load, output
voltage returns no higher than the original level, allowing
one output transient peak to be canceled over a load
application and release cycle.
For low current applications, a simple dropping resistor in
series with the output can provide fast, accurate adaptive
positioning. However, at high currents, the loss in a dropping
resistor becomes excessive. For example, a 50 A converter
with a 1.0 m resistor would provide a 50 mV change in
output voltage between no load and full load and would
dissipate 2.5 W. Lossless Adaptive Voltage Positioning
(AVP) is an alternative to using a droop resistor. Figure 20
shows how AVP works. The waveform labeled “normal”
shows a converter without AVP.
Adaptive Positioning
Limits
Adaptive Positioning
Normal
Fast
Slow
Figure 20. Adaptive Voltage Positioning
On the left, the output voltage sags when the output current
is stepped up and later overshoots when current is stepped
back down. With fast (ideal) AVP, the peak
to
peak
excursions are cut in half. In the slow AVP waveform, the
output voltage is not repositioned quickly enough after
current is stepped up and the upper limit is exceeded. The
controller can be configured to adjust the output voltage
based on the output current of the converter as shown in the
application diagram in Figure 1. The no
load positioning is
set internally to VID
19 mV, reducing the potential error
due to resistor and bias current mismatches. In order to
realize the AVP function, a resistor divider network is
connected between V
FB
, V
DRP
and V
OUT
. During no
load
conditions, the V
DRP
pin is at the same voltage as the V
FB
pin. As the output current increases, the V
DRP
pin voltage
increases proportionally. This drives the V
FB
voltage higher,
causing V
OUT
to “droop” according to a loadline set by the
resistor divider network. The response during the first few
microseconds of a load transient is controlled primarily by
power stage output impedance, and by the ESR and ESL of
the output filter. The transition between fast and slow
positioning is controlled by the total ramp size and the error
amp compensation. If the ramp size is too large or the error
amp too slow, there will be a long transition to the final
voltage after a transient. This will be most apparent with low
capacitance output filters.
Overvoltage Protection
Overvoltage Protection (OVP) in the Enhanced V
2
control topology is provided by operation of the
synchronous rectifiers. The control loop responds to an
overvoltage condition within 40 ns, causing the GATEx
output to shut off. The (external) MOSFET driver should
react normally to turn off the top MOSFET and turn on the
bottom MOSFET. This acts quickly to discharge the output
voltage and prevent damage to the load. The regulator will
remain in this state until the fault latch is reset by cycling
power at the V
CC
pin. If the voltage at the V
FFB
pin exceeds
200 mV above the VID voltage, the converter will latch off.
The OVP circuit begins monitoring the output voltage as
soon as the V
CC
voltage exceeds the UVLO threshold of the
part. The OVP circuit is then always active, regardless of
operating status.
Power Good
According to the latest specifications, the Power Good
(PWRGD) signal must be asserted when the output voltage
is within a window defined by the VID code, as shown in
Figure 21. The PWRLS pin is provided to allow the
PWRGD comparators to accurately sense the output
voltage. The effect of the PWRGD lower threshold can be
modified using a resistor divider from the output to PWRLS
to ground, as shown in Figure 22.
PWRGD
low
ééé
ééé
ééé
2.6
%
éééé
éééé
éééé
5.0
%
V
LOWER
VID + 80 mV
V
OUT
HIGH
LOW
PWRGD
+2.6%
+5.0%
Figure 21. PWRGD Assertion Window
PWRGD
low
PWRGD
high
Figure 22. Adjusting the PWRGD Threshold
V
OUT
R1
R2
PWRLS
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| NCP5318FTR2 | 功能描述:DC/DC 開關控制器 2/3/4 Phase Buck CPU RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
| NCP5318FTR2G | 功能描述:DC/DC 開關控制器 2/3/4 Phase Buck CPU RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
| NCP5322A | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC |
| NCP5322A/D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase Buck Controller with integrated Gate Drivers and 5-Bit DAC |
| NCP5322A_07 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC |
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