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參數(shù)資料
| 型號(hào)： | NCP5220MNR2G |
| 廠(chǎng)商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | 3−in−1 PWM Dual Buck and Linear Power Controller |
| 中文描述： | 2 A SWITCHING CONTROLLER, 566 kHz SWITCHING FREQ-MAX, DSO20 |
| 封裝： | 6 X 5 MM, LEAD FREE, DFN-20 |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大?。?/td> | 182K |
| 代理商： | NCP5220MNR2G |
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NCP5220
http://onsemi.com
10
DETAILED OPERATION DESCRIPTIONS
General
The NCP5220
3in1 PWM Dual Buck Linear DDR
Power Controller contains two high efficiency PWM
controllers and an integrated twoquadrant linear regulator.
The VDDQ supply is produced by a PWM switching
controller with two external NCh FETs. The VTT
termination voltage is an integrated linear regulator with
sourcing and sinking current capability which tracks at
VDDQ. The MCH core voltage is created by the secondary
switching controller.
The inclusion of softstart, supply undervoltage monitors
and thermal shutdown, makes this device a total power
solution for the MCH and DDR memory system. This device
is packaged in a DFN20.
ACPI Control Logic
The ACPI control logic is powered by the 5VDUAL
supply. It accepts external control at the SLP_S3 input and
internal supply voltage monitoring signals from two
UVLOs to decode the operating mode in accordance with
the state transition diagram in Figure 18.
These UVLOs monitor the external supplies, 5VDUAL
and 12VATX, through 5VDUAL and BOOT pins
respectively. Two control signals, _5VDUALGD and
_BOOTGD, are asserted when the supply voltages are good.
When the device is powered up initially, it is in the S5
shutdown mode to minimize the power consumption. When
all three supply voltages are good with SLP_S3 and SLP_S5
remaining HIGH, the device enters the S0 normal operating
mode. The transition of SLP_S3 from HIGH to LOW while
in the S0 mode, triggers the device into the S3 sleep mode.
In S3 mode the 12VATX supply collapses. On transition of
SLP_S3 from LOW to HIGH, the device returns to S0 mode.
The IC can reenter S5 mode by setting SLP_S5 LOW. A
timing diagram is shown in Figure 17.
Table 1 summarizes the operating states of all the
regulators, as well as the conditions of the output pins.
Internal Bandgap Voltage Reference
An internal bandgap reference is generated whenever
5VDUAL exceeds 2.7 V. Once this bandgap reference is in
regulation, an internal signal _VREFGD will be asserted.
S5 to S0 Mode PowerUp Sequence
The ACPI control logic is enabled by the assertion of
_VREFGD. Once the ACPI control is activated, the power
up sequence starts by waking up the 5VDUAL voltage
monitor block. If the 5VDUAL supply is within the preset
levels, the BOOT undervoltage monitor block is then
enabled. After 12VATX is ready and the BOOT UVLO is
asserted LOW, the ACPI control triggers this device from S5
shutdown mode into S0 normal operating mode by
activating the softstart of DDQ switching regulator,
providing SLP_S3 and SLP_S5 remain HIGH.
Once the DDQ regulator is in regulation and the softstart
interval is completed, the _InRegDDQ signal is asserted
HIGH to enable the VTT regulator as well as the V1P5
switching regulator.
DDQ Switching Regulator
In S0 mode the DDQ regulator is a switching synchronous
rectification buck controller driving two external power
NCh FETs to supply up to 20 A. It employs voltage mode
fixed frequency PWM control with external compensation
switching at 250kHz
±
13.2%. As shown in Figure 2, the
VDDQ output voltage is divided down and fed back to the
inverting input of an internal amplifier through the FBDDQ
pin to close the loop at VDDQ = VFBQ
×
(1 + R1/R2). This
amplifier compares the feedback voltage with an internal
reference voltage of 1.190 V to generate an error signal for
the PWM comparator. This error signal is compared with a
fixed frequency RAMP waveform derived from the internal
oscillator to generate a pulsewidthmodulated signal. This
PWM signal drives the external NCh FETs via the
TG_DDQ and BG_DDQ pins. External inductor L and
capacitor COUT1 filter the output waveform. When the IC
leaves the S5 state, the VDDQ output voltage ramps up at a
softstart rate controlled by the capacitor at the SS pin.
When the regulation of VDDQ is detected in S0 mode,
_INREGDDQ goes HIGH to notify the control block.
In S3 standby mode, the switching frequency is doubled
to reduce the conduction loss in the external NCh FETs.
Table 1. Mode, Operation and Output Pin Conditions
OPERATING CONDITIONS
OUTPUT PIN CONDITIONS
MODE
DDQ
VTT
MCH
TG_DDQ
BG_DDQ
TP_1P5
BG_1P5
S0
Normal
Normal
Normal
Normal
Normal
Normal
Normal
S3
Standby
HZ
OFF
Standby
Standby
Low
Low
S5
OFF
HZ
OFF
Low
Low
Low
Low
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相關(guān)代理商/技術(shù)參數(shù) |
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| NCP5222 | 制造商:ONSEMI 制造商全稱(chēng):ON Semiconductor 功能描述:High Performance Dual-Channel / Two-Phase Synchronous Buck Controller for Notebook Power System |
| NCP5222GEVB | 功能描述:電源管理IC開(kāi)發(fā)工具 NCP5222 EVAL BOARD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類(lèi)型:Battery Management 工具用于評(píng)估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| NCP5222MNR2G | 功能描述:DC/DC 開(kāi)關(guān)控制器 DUAL SYN BUCK CONTROLLER RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開(kāi)關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5228 | 制造商:ONSEMI 制造商全稱(chēng):ON Semiconductor 功能描述:Synchronous Buck Controller with Auto Power Saving |
| NCP5228MNTWG | 制造商:ON Semiconductor 功能描述:Notebook DDR Controller |
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