參數(shù)資料
型號(hào): NCP5218MNR2G
廠商: ON SEMICONDUCTOR
元件分類(lèi): 穩(wěn)壓器
英文描述: 2−in−1 Notebook DDR Power Controller
中文描述: 3 A SWITCHING CONTROLLER, 460 kHz SWITCHING FREQ-MAX, PDSO22
封裝: LEAD FREE, PLASTIC, DFN-22
文件頁(yè)數(shù): 22/31頁(yè)
文件大?。?/td> 463K
代理商: NCP5218MNR2G
NCP5218
http://onsemi.com
22
gain is obtained by adding the modulator and filter gain (in
dB) to the compensation gain (in dB)
.
The bandwidth is the
frequency at which the gain is 0 dB and the phase margin
is the difference between the close loop phase and 180
°
.
The goal of compensation is to achieve a stable close loop
system with the highest possible bandwidth, the gain
having
20 dB/decade slope at 0 dB gain crossing, and
sufficient phase margin for stability. The bandwidth of
close loop gain should be less than 50% of the switching
frequency and the compensation gain should be bounded
by the error amplifier open loop gain.
ADAPTIVE
RAMP
OSC
VDDQ
PWM
LOGIC
A
PWM
VIN
PGND
VREF
TGDDQ
SWDDQ
BGDDQ
PGND
COMP
FBDDQ
VDDQ
L
C2
C1
R3
C3
R4
R2
R1
COUT
VIN
Q2
Q1
CIN
ERROR
AMP
VBOOST
NCP5218
ESR
OUTPUT
FILTER
COMPENSATION
NETWORK
MODULATOR
VCCP
VRAMP
Figure 39. Voltage Mode Buck Converter with Modulator, LC filter and Type III Compensation
Modulator DC Gain can be calculated by:
GMOD(DC)
20 log
VIN
VRAMP
(eq. 20)
LC filter double pole and ESR zero break frequencies are
defined by:
fPLC
1
2
L
COUT
(eq. 21)
fZESR
1
2
ESR
COUT
(eq. 22)
Compensation network DC Gain can be calculated by the
equation:
GCOMP(DC)
20 logR3
R1
(eq. 23)
Type III compensation poles and zeros break frequencies
are defined by the below equations:
fZ1
1
2
R3
C2
(eq. 24)
fP1
1
2
R3
C1
C1
C2
C2
(eq. 25)
fZ2
1
2
(R1
R4)
C3
(eq. 26)
fP2
1
2
R4
C3
(eq. 27)
80
100
Open Loop Error
Amp Gain
Compensation
Gain
Closed Loop Gain
Modulator & Filter Gain
60
40
20
0
20
40
60
G
10
100
1 k
10 k
100 k
1 M
10 M
f
Z1
f
Z2
f
P1
f
P2
f
ZESR
f
PLC
20 log
20 log
R3
R1
VIN
VRAMP
FREQUENCY (Hz)
Figure 40. Asymptotic Bode Plot of the Converter Gain
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