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參數(shù)資料
| 型號(hào)： | NCP5218 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 2−in−1 Notebook DDR Power Controller |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 463K |
| 代理商： | NCP5218 |
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NCP5218
http://onsemi.com
16
efficiency of the V
DDQ
regulator at light loads. The
switching frequency can be reduced smoothly until it
reaches the minimum frequency at about 15 kHz.
Therefore, perceptible audible noise can be avoided at light
load condition.
In power
saving mode, the low
side MOSFET is turned
off after the detection of negative inductor current and the
converter cannot sink current. The power
saving mode can
be disabled by pulling the FPWM pin to ground. Then, the
converter operates in forced
PWM mode with fixed
switching frequency and ability to sink current.
Fault Protection of V
DDQ
Regulator
During state S0 and S3, external resistor (RL1) between
OCDDQ and V
IN
sets the overcurrent trip threshold for the
high
side switch. An internal 31 A current sink (IOC) at
OCDDQ pin establishes a voltage drop across this resistor
and develops a voltage at the non
inverting input of the
current limit comparator. The voltage at the non
inverting
input is compared to the voltage at SWDDQ pin when the
high
side gate drive is high after a fixed period of blanking
time (150 ns) to avoid false current limit triggering. When
the voltage at SWDDQ is lower than that at the
non
inverting input for 4 consecutive internal clock
cycles, an overcurrent condition occurs, during which, all
outputs will be latched off to protect against a
short
to
ground condition on SWDDQ or VDDQ. The IC
will be reset once VCCA or VDDQEN is cycled.
Feedback Compensation of V
DDQ
Regulator
The compensation network is shown in Figures 2 and 39.
V
TT
Active Terminator in Normal Mode (S0)
The V
TT
active terminator is a two
quadrant linear
regulator with two internal N
channel power FETs. It is
capable of sinking and sourcing at least 1.5 A continuous
current and up to 2.4 A transient peak current. It is activated
in normal mode in state S0 when the VTTEN pin is HIGH
and VDDQ is in regulation. Its input power path is from
VDDQ with the internal FETs gate drive power derived
from VCCA. The V
TT
internal reference voltage is derived
from the DDQREF pin. The VTT output is set to VDDQ/2
when V
TT
output is connecting to the FBVTT pin directly.
This regulator is stable with only a minimum 20 F output
capacitor. The V
TT
regulator will have an internal
soft
start when it is transited from disable to enable.
During the V
TT
soft
start, a current limit is used as a current
source to charge up the V
TT
output capacitor. The current
limit is initially 1.0 A during V
TT
soft
start. It is then
increased to 2.5 A after 128 internal clock cycles which is
typically 0.32 ms.
V
TT
Active Terminator in Standby Mode (S3)
V
TT
output is high
impedance in S3 mode.
Fault Protection of V
TT
Active Terminator
To provide protection for the internal FETs, bidirectional
current limit is implemented, preset at the minimum of
2.5 A magnitude.
Thermal Consideration of V
TT
Active Terminator
The V
TT
terminator is designed to handle large transient
output currents. If large currents are required for very long
duration, then care should be taken to ensure the maximum
junction temperature is not exceeded. The 5x6 DFN22 has
a thermal resistance of 35
°
C/W (dependent on air flow,
grade of copper, and number of vias).
In order to take full
advantage from this thermal capability of this package, the
thermal pad underneath must be soldered directly onto a
PCB metal substrate to allow good thermal contact. It is
recommended that PCB with 2 oz. copper foil is used and
there should have 6 to 8 vias with 0.6 mm hole size
underneath the package’s thermal pad connecting the top
layer metal to the bottom layer metal and the internal layer
metal substrates of the PCB.
VTTREF Output
The V
TTREF
output tracks V
DDQREF
/2 at
It has source current capability of up to 15 mA. V
TTREF
should be bypassed to analog ground of the device by
1.0 F ceramic capacitor for stable operation. The V
TTREF
is turned on as long as V
DDQREF
is pulled high. In S0 mode,
V
TTREF
soft
starts with V
DDQ
and tracks V
DDQREF
/2. In
S3 mode, V
TTREF
is kept on with V
DDQ
. V
TTREF
is turned
off only in S4/S5 like V
DDQ
output.
2% accuracy.
Output Voltages Sensing
The V
DDQ
output voltage is sensed across the FBDDQ
and AGND pins. FBDDQ should be connected through a
feedback resistor divider to the VDDQ point of regulation
which is usually the local V
DDQ
bypass capacitor for load.
The AGND should be connected directly through a sense
trace to the remote ground sense point which is usually the
ground of local V
DDQ
bypass capacitor for load.
The V
TT
output voltage is sensed between the FBVTT
and VTTGND pins. The FBVTT should be connected to
the V
TT
regulation point, which is usually the V
TT
local
bypass capacitor, via a direct sense trace. The VTTGND
should be connected via a direct sense trace to the ground
of the V
TT
local bypass capacitor for load.
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| NCP5218MNR2G | 功能描述:電壓模式 PWM 控制器 2IN1 NOTEBK DDR CNTL RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| NCP5220 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3−in−1 PWM Dual Buck and Linear Power Controller |
| NCP5220AMNR2 | 功能描述:DC/DC 開關(guān)控制器 3-in-1 PWM Dual Buck RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5220AMNR2G | 功能描述:DC/DC 開關(guān)控制器 ANA DDR PWER CNTRLR RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5220MNR2 | 功能描述:DC/DC 開關(guān)控制器 3-in-1 PWM Dual Buck RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
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