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參數(shù)資料
| 型號： | NCP5211DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Low Voltage Synchronous Buck Controller |
| 中文描述： | 1 A SWITCHING CONTROLLER, 900 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | LEAD FREE, SOIC-14 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 132K |
| 代理商： | NCP5211DR2G |
NCP5211
http://onsemi.com
9
the design must first predict the MOSFET power dissipation.
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
at the highest ambient temperature. Power dissipation has two
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
nonoverlap time of the gate drivers.
For the upper or control MOSFET, the power dissipation
can be approximated from:
PD,CONTROL
(ILo,MAX
(Qoss2
(IRMS,CNTL2
QswitchIg
VIN
fSW)
RDS(on))
VIN
(VIN
fSW)
QRR
fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the losses associated with
the
control and synchronous
MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous
MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
Where I
RMS,CNTL
is the RMS value of the trapezoidal
current in the control MOSFET:
IRMS,CNTL
D
[(ILo,MAX2
ILo,MIN2) 3]1 2
ILo,MAX
ILo,MIN
I
Lo,MAX
is the maximum output inductor current:
ILo,MAX
IO,MAX2
ILo2
I
Lo,MIN
is the minimum output inductor current:
ILo,MIN
IO,MAX2
I
O,MAX
is the maximum converter output current.
D is the duty cycle of the converter:
ILo2
D
VOUTVIN
I
Lo
is the peaktopeak ripple current in the output
inductor of value Lo:
ILo
(VIN
VOUT)
D (Lo
fSW)
R
DS(on)
is the ON resistance of the MOSFET at the
applied gate drive voltage.
Q
switch
is the post gate threshold portion of the
gatetosource charge plus the gatetodrain charge. This
may be specified in the data sheet or approximated from the
gatecharge curve as shown in the Figure 5.
Qswitch
Qgs2
Qgd
I
D
V
GATE
V
DRAIN
Q
GD
Q
GS2
Q
GS1
V
GS_TH
Figure 5. MOSFET Switching Characteristics
I
g
is the output current from the gate driver IC.
V
IN
is the input voltage to the converter.
f
sw
is the switching frequency of the converter.
Q
G
is the MOSFET total gate charge to obtain R
DS(on)
.
Commonly specified in the data sheet.
V
g
is the gate drive voltage.
Q
RR
is the reverse recovery charge of the
lower
MOSFET.
Q
oss
is the MOSFET output charge specified in the data
sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
PD,SYNCH
(IRMS,SYNCH2
(Vfdiode
IO,MAX2
RDS(on))
t_nonoverlap
fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate nonoverlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
IRMS,SYNCH
[(ILo,MAX2
where:
Vf
diode
is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the nonoverlap time between the upper
and lower gate drivers to prevent cross conduction. This
time is usually specified in the data sheet for the control
IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature
1
D
ILo,MAX
ILo,MIN
ILo,MIN2) 3]1 2
T
(TJ
TA) PD
where;
T
is the total thermal impedance (
JC
+
SA
).
JC
is the junctiontocase thermal impedance of the
MOSFET.
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