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參數(shù)資料
| 型號： | NCP5210MNR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3-in-1 PWM Dual Buck and Linear DDR Power Controller |
| 中文描述： | DUAL SWITCHING CONTROLLER, 550 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | 6 X 5 MM, PLASTIC, QFN-20 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大小： | 183K |
| 代理商： | NCP5210MNR2 |
NCP5210
http://onsemi.com
10
DETAILED OPERATION DESCRIPTIONS
General
The NCP5210
3In1 PWM Dual Buck Linear DDR
Power Controller contains two high efficiency PWM
controllers and an integrated twoquadrant linear regulator.
The VDDQ supply is produced by a PWM switching
controller with two external NCh FETs. The VTT
termination voltage is an integrated linear regulator with
sourcing and sinking current capability which tracks at 1/2
VDDQ. The MCH core voltage is created by the secondary
switching controller.
The inclusion of softstart, supply undervoltage monitors,
short circuit protection and thermal shutdown, makes this
device a total power solution for the MCH and DDR
memory system. This device is housed in a thermal
enhanced spacesaving QFN20 package.
ACPI Control Logic
The ACPI control logic is powered by the 5VDUAL
supply. External control is applied to the high impedance
CMOS input labeled BUF_CUT. This signal and two
internal under voltage detectors are used to determine the
operating mode according to the state diagram in Figure 17.
These UVLOs monitor the external supplies, 5VDUAL
and 12VATX, through 5VDUAL and BOOT pins
respectively. Two control signals, _5VDUALGD and
_BOOTGD, are asserted when the supply voltages are good.
The device is powered up initially in the S5 shutdown
mode to minimize the power consumption. When all three
supply voltages are good and BUF_CUT is LOW, the device
enters the S0 normal operating mode. Transition of
BUF_CUT from LOW to HIGH in S0 mode triggers the
device into S3 sleep mode. In S3 mode 12VATX supply
collapses. When BUF_CUT is deasserted the state will
change back to S0 mode. The IC can reenter S5 mode by
removing one of the supplies during S0 mode. It should be
noted that transitions from S3 to S5 or vice versa are not
allowed. A timing diagram is shown in Figure 16.
Table 1 summarizes the operating states of all the
regulators, as well as the conditions of output pins.
Internal Bandgap Voltage Reference
An internal bandgap reference is generated whenever
5VDUAL exceeds 2.7 V. Once this bandgap reference is in
regulation, an internal signal _VREFGD is asserted.
S5ToS0 Mode PowerUp Sequence
The ACPI control logic is enabled by the assertion of
_VREFGD. Once the ACPI control is activated, the
powerup sequence starts by waking up the 5VDUAL
voltage monitor block. If the 5VDUAL supply is within the
preset levels, the BOOT under voltage monitor block is then
enabled. After 12VATX is ready and the BOOT UVLO is
asserted LOW, the ACPI control triggers this device from S5
shutdown mode into S0 normal operating mode by
activating the softstart of DDQ switching regulator,
providing BUF_CUT remaining LOW.
Once the DDQ regulator is in regulation and the softstart
interval is completed, the _INREGDDQ signal is asserted
HIGH to enable the VTT regulator as well as the V1P5
switching regulator.
DDQ Switching Regulator
In S0 mode the DDQ regulator is a switching synchronous
rectification buck controller driving two external power
NCh FETs to supply up to 20 A. It employs voltage mode
fixed frequency PWM control with external compensation
switching at 250kHz
±
13.2%. As shown in Figure 2, the
VDDQ output voltage is divided down and fed back to the
inverting input of an internal amplifier through the FBDDQ
pin to close the loop at VDDQ = VFBQ
×
(1 + R1/R2). This
amplifier compares the feedback voltage with an internal
reference voltage of 1.190 V to generate an error signal for
the PWM comparator. This error signal is compared with a
fixed frequency RAMP waveform derived from the internal
oscillator to generate a pulsewidthmodulated signal. The
PWM signal drives the external NCh FETs via the
TG_DDQ and BG_DDQ pins. External inductor L and
capacitor COUT1 filter the output waveform. When the IC
leaves the S5 state, the VDDQ output voltage ramps up at a
softstart rate controlled by the capacitor at the SS pin.
When the regulation of VDDQ is detected in S0 mode,
_INREGDDQ goes HIGH to notify the control block.
In S3 standby mode, the switching frequency is doubled
to reduce the conduction loss in the external NCh FETs.
Table 1. Mode, Operation and Output Pin Condition
OPERATING CONDITIONS
OUTPUT PIN CONDITIONS
MODE
DDQ
VTT
MCH
TGDDQ
BGDDQ
TP_1P5
BG_1P5
S0
Normal
Normal
Normal
Normal
Normal
Normal
Normal
S3
Standby
HZ
OFF
Standby
Standby
Low
Low
S5
OFF
HZ
OFF
Low
Low
Low
Low
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NCP5210MNR2G | 功能描述:DC/DC 開關(guān)控制器 3-in-1 DDR Power RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5211 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Low Voltage Synchronous Buck Controller |
| NCP5211A | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Low Voltage Synchronous Buck Controller |
| NCP5211A/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage Synchronous Buck Controller |
| NCP5211AD | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Low Voltage Synchronous Buck Controller |
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