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參數資料
| 型號： | NCP500SQL50T1G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | 150 mA CMOS Low Noise Low−Dropout Voltage Regulator |
| 中文描述： | 5 V FIXED POSITIVE LDO REGULATOR, 0.18 V DROPOUT, PDSO6 |
| 封裝： | 2 X 2.2 MM, LEAD FREE, DFN-6 |
| 文件頁數： | 16/20頁 |
| 文件大小： | 153K |
| 代理商： | NCP500SQL50T1G |
NCP500
http://onsemi.com
16
Output
1
2
3
5
4
Input
1.0 F
1.0 F
Q1
R
5.6 V
A regulated output can be achieved with input voltages that ex-
ceed the 6.0 V maximum rating of the NCP500 series with the
addition of a simple preregulator circuit. Care must be taken
to prevent Q1 from overheating when the regulated output
(V
out
) is shorted to G
nd.
Output
1
2
3
5
4
Input
1.0 F
1.0 F
Output
1
2
3
5
4
Enable
1.0 F
1.0 F
C
0
3
3
2
1
0
80
2.5
90
40
30
110
Time (ms)
V
o
O
2
1.5
20
4
1
0.5
0
100
70
60
50
10
E
T
A
= 25
°
C
V
in
= 3.4 V
V
out
= 2.8 V
R = 1.0 M
C = 1.0 F
R = 1.0 M
C = 0.1 F
No Delay
If a delayed turnon is needed during power up of several volt-
ages then the above schematic can be used. Resistor R, and
capacitor C, will delay the turnon of the bottom regulator. A
few values were chosen and the resulting delay can be seen in
Figure 33.
The graph shows the delay between the enable signal and
output turnon for various resistor and capacitor values.
R
Figure 32. Delayed Turnon
Figure 33. Delayed Turnon
Figure 34. Input Voltages Greater than 6.0 V
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