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參數(shù)資料
| 型號： | NCP4331DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Synchronous Buck Controller for High Efficiency Post Regulation |
| 中文描述： | SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | LEAD FREE, SOIC-16 |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 195K |
| 代理商： | NCP4331DR2G |
NCP4331
http://onsemi.com
13
As portrayed in Figure 21, the post-regulator controls the
energy to be drawn from the power source V
in
by adjusting
the time during which the high-side MOSFET is on. This
conduction time is modulated by adjusting the leading edge
of the high side drive while the trailing edge stays
synchronized to the input voltage V
in
.
As in a traditional buck, the post-regulated output voltage
is given by the following equation:
V
out
d
n
N
S
N
P
V
inforward
(eq. 2)
Where: d
n
is the duty cycle of the post-regulator n.
d
n
< d
F
since (N
S
/N
P
(V
in
)
forward
) is available only during
the forward converter on-time and that anyway, the
high-side MOSFET cannot be turn on as long as V
in
is low
(i.e., during the forward off-time).
Post-regulated output voltages are then necessarily lower
than the main regulated one. However, the NCP4331
scheme allows d
n
to nearly equal d
f
so that if necessary, a
post-regulated output voltage (Vout
n
) can be very closed the
main one (V
out1
).
Sequencing and Regulation Block
The following timing diagram portrays the sequencing.
Figure 22. Timing Diagram
TIME
TIME
TIME
TIME
TIME
TIME
TIME
High-Side Driver
Low-Side Driver
Sum
(V
ramp
+ EA
out
)
V
ramp
(C
ramp
Timing Ramp)
Internal Reset Signal
V
in
(Post-Regulator
Input Voltage)
The Low-Side and
High-Side Trans‐
itions are Delayed
until V
in
is High.
70 ns
70 ns
EA
out
(Error
Amplifier Out
250 ns
Sequencing and Overlapping
Figure 22 portrays the sequencing of a NCP4331 driven
post-regulator.
The high-side driver turns on (off) after some delay just
after the low-side has switched off (on). More precisely, the
high-side MOSFET:
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