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參數(shù)資料
| 型號(hào)： | NCP4326DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Secondary Controller for Multi−Output Quasi−Resonant Switchmode Power Supplies |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | LEAD FREE, SOIC-16 |
| 文件頁數(shù)： | 26/30頁 |
| 文件大小： | 432K |
| 代理商： | NCP4326DR2G |
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NCP4326
http://onsemi.com
26
Standby Pin Feature Description
The standby pin enables or disables the controller in order
to save some power when the power supply is in standby
mode. In standby mode all the internal power supplies and
references are shut down, except the V
DD1
and the voltage
reference connected to the shunt regulator. The shunt
regulator bloc works during the standby mode for supplying
the feedback to the primary controller.
When the standby pin is released the both drivers are kept
in OFF state during T
stby_off
time to prevent any parasitic
switches on the driver before the internal power ON of the
controller is fully finished.
Practically the internal standby signal for the driver is
delayed and in the mean time the internal power waking up
is done.
DRV1
VOLTAGE
REFERENCE
GND
STBY
Vcc OK
Vcc OK
1V25
GND
Figure 49. Standby Delay Definition
2V5
+
2V5
SoftStart
STBY
DELAY
V
CC
V
CC
V
CC
UVLO
V
CC
V
DD1
V
DD1
V
DD
V
DD1
*V
DD
is not available in standby mode
**V
DD1
is available all the time
Synchronization Pin
The NCP4326 needs to be synchronized with the primary
controller, a dedicated pin ensures this function just by
sensing a secondary winding voltage and filtering it.
The RC network (Rsync1 and Csync) filters the secondary
winding and Rsync2 limits the current through the internal
zener diode when the voltage exceeds the zener clamp level
or when the zener conduct in forward mode (when the
voltage winding is negative).
+
GND
Sync
Ct
ICt
GND
Enable
4V0
1V6
GND
GND
Ct
Csync
Rsync1
Rsync2
GND
Flyback transformer
D1
Mag
GND
NCP4326
Figure 50. Synchronization Pin Wiring
V
DD
V
DD
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