參數(shù)資料
型號： NCP1601BDR2G
廠商： ON Semiconductor
文件頁數(shù)： 14/19頁
文件大?。?/td> 257K
描述： IC PFC CTRL CRM/TRANSITION 8SOIC
產(chǎn)品變化通告： NCP1601BDR2G Discontinuation 11/May/2012
標(biāo)準(zhǔn)包裝： 1
模式： 臨界傳導(dǎo)（CRM），間歇式（轉(zhuǎn)換）
頻率 - 開關(guān)： 58kHz
電流 - 啟動： 17µA
電源電壓： 9.6 V ~ 18 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOICN
包裝： 剪切帶 (CT)
其它名稱： NCP1601BDR2GOSCT
NCP1601A, NCP1601B
http://onsemi.com
14
Based on the CS pin (Pin 4) characteristics in Figure 15,
Figure 33 is studied. When the inductor current is exactly
zero (i.e., I
L(ZCD)
= 0), the ideal ZCDpoint inthe Figure is
reached where R
S
is R
S(ZCD)
(536 ?typical). Considering
the tolerance, the actual sense resistor R
S
is needed to be
higher than the ideal value of R
S(ZCD)
to ensure that zero
current signal is generated when sense current is smaller
than the ZCD threshold (i.e., I
S
< I
S(ZCD)
). That is,
R
S
> R
S(ZCD)
=
V
S(ZCD)
I
S(ZCD)
(eq.15)
The higher value of R
S
makes the longer distance
between the operating and ideal ZCD points in Figure 33.
Hence,  R
S
has  to  be  as  low  as  possible.  The  best
recommended value of R
S
is therefore the maximum of
R
S(ZCD)
which is 1 k?
Now that the R
S
is set at a particular value which is
greater than R
S(ZCD)
. From (eq.13), the operating lines in
(eq.16) with different inductor currents I
L
of (eq.13) are
studied.
V
S
= R
S
 R
CS
I
L
(eq.16)
TheseoperatinglinesareaddedinFigure33toformulate
Figure 34. When the inductor current I
L
is lower than
I
L(ZCD)
,thesensecurrentI
S
islowerthanI
S(ZCD)
andhence
the zero current signal is generated.
Figure 34. CS Pin Characteristic with Different
Inductor Current
I
S(ZCD)
V
S(ZCD)
V
S
Operating
ZCD point
I
S
Best
ZCD
point
I
L
= I
L(ZCD)
I
L
> I
L(ZCD)
I
L
= 0
ItisnotedinFigure34and(eq.16)thatwhenthe (R
CS
I
L
)
termissmallertheerrorordistancebetweenthelinestothe
line I
L
= 0 is smaller. Therefore, the value of the current
sense resistor R
CS
is also recommended to be as small as
possibletominimizetheerrorinthezerocurrentdetection.
Overcurrent Protection (OCP)
Overcurrent protection is reached when I
S
is higherthan
I
S(OCP)
(200 mA typical). The offset voltage of the CS pin
is V
S(OCP)
(3.2 mV typical) in this condition. That is
(eq.17)
I
L(OCP)
=
R
S
I
S(OCP)
 V
S(OCP)
R
CS
When overcurrent protection threshold is reached, the
Drive Output of the device goes low.
Oscillator / Synchronization Block
Figure 35. Oscillator / Synchronization Block
Oscillator Clock
S
R
Q
Zero Current
Turn on
MOSFET
- -
+
5 V/3.5 V
Osc
delay
0
5
1
45 mA
94 mA
&
Figure 36. Oscillator Block Timing Diagram
time
clock
inductor
clock latch
(latch set signal)
Discontinuous mode
Critical mode
(latch output)
current
clock edge
The NCP1601 is a DCM / CRM PFC controller. Inorder
to keep the operation in DCM or CRM only, the Drive
Output cannot turn on as long as there is some inductor
currentflowingthroughthecircuit. Hence,the zerocurrent
signal is provided to the oscillator / synchronization block
in Figure 35. An input comparator monitors the Osc pin
(Pin 5) voltage and generates a clock signal. The negative
edge of the clock signal is stored in a RS latch. When zero
currentisdetected,theRSlatchwillberesetandasetsignal
issenttotheoutputdrivelatchwhichturnsontheMOSFET
in the PFC boost circuit. Figure 36 illustrates a typical
timing diagram of the oscillator block.
Oscillator Mode
The Osc pin(Pin5) isconnected toan externalcapacitor
C
osc
. When the voltage of this pin is above V
sync(H)
(5 V
typical), the pin sinks a current I
odch
(94  45 = 49 mA
typical) and the external capacitor C
osc
discharges. When
the voltage reachesV
sync(L)
(3.5Vtypical),the pinsources
a current I
och
(45 mA typical) and the external capacitor
C
osc
is charged. It is noted that there is a typical 300 ns
propagation delay and the 3.5 V and 5 V threshold
conditions are measured on 220 pF C
osc
capacitor. Hence,
the actual oscillator hysteresis is a slightly smaller.
Figure 37. Oscillator Mode Timing Diagram in DCM
Osc pin
voltage
Osc clock
Clock edge
Drive output
(DCM)
5 V
3.5 V
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