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參數(shù)資料
| 型號： | NCP1081DEG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 257K |
| 描述： | IC CONV CTLR POE-PD 40W 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 類型： | 以太網(wǎng)供電開關(guān)（PoE） |
| 應(yīng)用： | 遠(yuǎn)程外設(shè)（工業(yè)控制，相機(jī)，數(shù)據(jù)訪問） |
| 內(nèi)部開關(guān)： | 是 |
| 電流限制： | 1.1A |
| 電源電壓： | 0 V ~ 57 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP-EP |
| 包裝： | 管件 |
NCP1081
http://onsemi.com
9
Table 3. OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Units
Conditions
VDDH REGULATOR
VDDH_reg
Regulator output voltage
(Notes 10 and 11)
Ivddh_load + Ivddl_load < 10 mA
with
0 < Ivddl_load < 2.25 mA
8.4
9
9.6
V
VDDH_Off
Regulator turnoff voltage
VDDH_reg
+ 0.5 V
V
For information only
VDDH_lim
VDDH regulator current limit
(Notes 10 and 11)
13
26
mA
VDDH_Por_R
VDDH POR level (rising)
7.3
8.3
V
VDDH_Por_F
VDDH POR level (falling)
6
7
V
VDDH_ovlo
VDDH overvoltage level (rising)
16
18.5
V
VDDL REGULATOR
VDDL_reg
Regulator output voltage
(Notes 10 and 11)
0 < Ivddl_load < 2.25 mA
with
Ivddh_load + Ivddl_load < 10 mA
3.05
3.3
3.55
V
VDDL_Por_R
VDDL POR level (rising)
VDDL
0.2
VDDL
0.02
V
VDDL_Por_F
VDDL POR level (falling)
2.5
2.9
V
GATE DRIVER
Gate_Tr
GATE rise time (1090%)
50
ns
Cload = 2 nF, VDDHreg = 9 V
Gate_Tf
GATE fall time (9010%)
50
ns
Cload = 2 nF, VDDHreg = 9 V
PWM COMPARATOR
VCOMP
COMP control voltage range
1.3
3
V
For information only
ERROR AMPLIFIER
Vbg_fb
Reference voltage
1.15
1.2
1.25
V
Voltage with respect to ARTN
Av_ol
DC open loop gain
80
dB
For information only
GBW
Error amplifier GBW
1
MHz
For information only
SOFTSTART
Vss
Softstart voltage range
1.15
V
Vss_r
Softstart low threshold (rising edge)
0.35
0.45
0.55
V
Iss
Softstart source current
3
5
7
mA
CURRENT LIMIT COMPARATOR
CSth
CS threshold voltage
324
360
396
mV
Tblank
Blanking time
100
ns
For information only
OSCILLATOR
DutyC
Maximum duty cycle
80%
Fixed internally
Frange
Oscillator frequency range
100
500
kHz
F_acc
Oscillator frequency accuracy
?5
%
10.Power dissipation must be considered. Load on VDDH and VDDL must be limited especially if VDDH is not powered by an auxiliary winding.
11.Ivddl_load = current flowing out of the VDDL pin.
Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET
gate capacitance).
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