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參數(shù)資料
| 型號： | NCN6001DTBR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 標準包裝： | 1 |
| 應用： | 智能卡 |
| 接口： | 微控制器 |
| 電源電壓： | 2.75 V ~ 5.5 V |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 標準包裝 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | NCN6001DTBR2OSDKR |
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NCN6001
http://onsemi.com
20
SPI PORT
The
product
communicates
to
the
external
microcontroller by means of a serial link using a
Synchronous Port Interface protocol, the CLK_SPI being
Low or High during the idle state. The NCN6001 is not
intended to operate as a Master controller, but execute
commands coming from the MPU.
The CLK_SPI, the CS and the MOSI signals are under the
microcontroller’s responsibility. The MISO signal is
generated by the NCN6001, using the CLK_SPI and CS
lines to synchronize the bits carried out by the data byte. The
system runs with two internal registers associated with the
MOSI and MISO data:
WRT_REG is a write only register dedicated to the MOSI
data.
READ_REG is a read only register dedicated to the MISO
data.
Figure 12. Basic SPI Timings and Protocol
MPU Asserts Chip Select
NCN6001 Reads Bit
MPU Reads Bit
RST_COUNTER
MOSI
SPI_CLK
CS
MISO
tclr
MPU Enables
Clock
MPU Sends Bit
NCN6001 Sends Bit
from READ_REG
When the CS line is High, no data can be written or read
on the SPI port. The two data lines becomes active when
CS = Low, the internal shift register is cleared and the
communication is synchronized by the negative going edge
of the CS signal. The data present on the MOSI line is
considered valid on the negative going edge of the CLK_SPI
clock and is transferred to the shift register on the next
positive edge of the same CLK_SPI clock.
To accommodate the simultaneous MISO transmit, an
internal logic identifies the chip address on the fly (reading
and decoding the three first bits) and validates the right data
present on the line. Consequently, the data format is MSB
first to read the first three signal as bits B5, B6 and B7. The
chip address is decoded from this logic value and validates
the chip according to the C4 and C8 conditions (Figure 13).
Figure 13. Chip Address Decoding Protocol and MISO Sequence
MPU Asserts Chip Set
MISO Line = High Impedance
ADDRESS
DECODE
MOSI
SPI_CLK
CS
MISO
MPU Enables Clock
B7
B6
B5
B4
B3
B2
B1
B0
LSB
COMMAND AND CONTROL
CHIP
ADDRESS
The Chip Address is decoded on the third clock pulse.
The MISO signal is activated and data transferred
MSB
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