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參數(shù)資料
| 型號(hào)： | NBSG72AMNR2 |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 7/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWITCH 2X2 16QFN |
| 產(chǎn)品變化通告： | LTB Notification 06/Feb/2008 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 功能： | 交叉點(diǎn)開(kāi)關(guān) |
| 電路： | 1 x 2:2 |
| 電壓電源： | 雙電源 |
| 電壓 - 電源，單路/雙路(±)： | ±2.38 V ~ 3.47 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
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NBSG72A
http://onsemi.com
2
Figure 1. QFN16 Pinout (Top View)
VEE D1
D1 VTD1
VCC Q0
Q0 OLS
VCC
Q1
SELB
VTD0
D0
SELA
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG72A
Exposed Pad (EP)
Table 1. PIN DESCRIPTION
Pin No.
Name
I/O
Description
1
VTD0
2
D0
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
Inverted Differential Input 0.
3
D0
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
Noninverted Differential Input 0.
4
SELA
LVECL, LVCMOS
Input
Select Logic Input A. Internal 75 kW Pulldown to VEE.
5
VEE
Negative Supply. All VEE Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
6
D1
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
Inverted Differential Input 1.
7
D1
LVDS, CML, ECL,
LVTTL, LVCMOS
Input
Noninverted Differential Input 1.
8
VTD1
9
SELB
LVECL, LVCMOS
Input
Select Logic Input B. Internal 75 kW Pulldown to VEE.
10
Q1
RSECL Output
Noninverted Differential Output.
11
Q1
RSECL Output
Inverted Differential Output.
12
VCC
Positive Supply. All VCC Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
13
OLS
(Note 2)
Input
Input Pin for Output Level Select (OLS) See Table 3.
14
Q0
RSECL Output
Noninverted Differential Output Typically Terminated with 50 W Resistor to
VTT = VCC 2.0 V.
15
Q0
RSECL Output
Inverted Differential Output Typically Terminated with 50 W Resistor to
VTT = VCC 2.0 V.
16
VCC
Positive Supply. All VCC Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
EP
The Exposed Pad (EP) and the QFN16 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be attached
to a heatsinking conduit. The pad is not electrically connected to the die but may be
electrically and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pins (VTD0, VTD1) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to selfoscillation.
2. When an output level of 400 mV is desired and VCC VEE > 3.0 V, 2 kW resistor should be connected from OLS pin to VEE.
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