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參數(shù)資料
| 型號： | NBSG16MMN |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RCVR/DRVR CML 2.5V/3.3V 16QFN |
| 產(chǎn)品變化通告： | LTB Notification 06/Feb/2008 |
| 標(biāo)準(zhǔn)包裝： | 123 |
| 類型： | 收發(fā)器 |
| 應(yīng)用： | 儀表 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 管件 |
| 其它名稱： | NBSG16MMNOS |
NBSG16M
http://onsemi.com
2
VCC NC VEE VEE
VCC VBB VEE VEE
VCC
Q
VCC
VTD
D
VTD
5
678
16
15
14
13
12
11
10
9
1
2
3
4
NBSG16M
Exposed Pad (EP)
Figure 1. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTD
2
D
LVDS, CML, ECL, LVTTL,
LVCMOS Input
Inverted Differential Input (Note 3)
3
D
LVDS, CML, ECL, LVTTL,
LVCMOS Input
Noninverted Differential Input. (Note 3)
4
VTD
5
VCC
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guar-
antee proper operation.
6
NC
No Connect (Note 1)
7
VEE
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guar-
antee proper operation.
8
VEE
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guar-
antee proper operation.
9
VCC
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guar-
antee proper operation.
10
Q
CML Output
Noninverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2)
11
Q
CML Output
Inverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2)
12
VCC
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guar-
antee proper operation.
13
VEE
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guar-
antee proper operation.
14
VEE
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guar-
antee proper operation.
15
VBB
Internally Generated ECL Reference Output Voltage
16
VCC
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guar-
antee proper operation.
EP
The Exposed Pad (EP) and the QFN16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat
sinking conduit. The pad is not electrically connected to the die but may be electrically and
thermally connected to VEE on the PC board.
1. The NC pins are electrically connected to the die and MUST be left open.
2. CML outputs require 50 W receiver termination resistor to VCC for proper operation.
3. In the differential configuration when the input termination pin (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to selfoscillation.
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