VCC = 0 V; V<" />
參數(shù)資料
型號(hào)： NBSG16BAR2
廠商： ON Semiconductor
文件頁(yè)數(shù)： 11/12頁(yè)
文件大小： 0K
描述： IC RCVR/DRVR RSECL SIGE 16FCBGA
產(chǎn)品變化通告： Product Discontinuation 20/Aug/2008
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 收發(fā)器
應(yīng)用： 儀表
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-LBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 16-FCBGA（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： NBSG16BAR2OSDKR
NBSG16
http://onsemi.com
8
Table 8. AC CHARACTERISTICS for FCLGA16
VCC = 0 V; VEE = 3.465 V to 2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 4. fmax/JITTER) (Note 17)
10.7
12
10.7
12
10.7
12
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
90
110
130
100
120
140
105
125
145
ps
tSKEW
Duty Cycle Skew (Note 18)
3
15
3
15
3
15
ps
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
PeaktoPeak Data Dependent Jitter
fin < 10 Gb/s
0.2
TBD
1
0.2
TBD
1
0.2
TBD
1
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 19)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times @ 1 GHz
Q, Q
(20% 80%)
30
45
75
20
40
65
20
40
65
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V. Input edge rates 40 ps (20% 80%).
18.See Figure 6. tskew = |tPLH tPHL| for a nominal 50% differential clock input waveform.
19.VINPP(max) cannot exceed VCC VEE
Table 9. AC CHARACTERISTICS for QFN16
VCC = 0 V; VEE = 3.465 V to 2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 4. fmax/JITTER) (Note 20)
10.7
12
10.7
12
10.7
12
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
90
110
130
100
120
140
95
125
145
ps
tSKEW
Duty Cycle Skew (Note 21)
3
15
3
15
3
15
ps
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
PeaktoPeak Data Dependent Jitter
fin < 10 Gb/s
0.2
TBD
2
0.2
TBD
2
0.2
TBD
2
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 22)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times @ 1 GHz
Q, Q
(20% 80%)
20
30
50
20
30
50
20
30
50
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V. Input edge rates 40 ps (20% 80%).
21.See Figure 6. tskew = |tPLH tPHL| for a nominal 50% differential clock input waveform.
22.VINPP(max) cannot exceed VCC VEE
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