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參數(shù)資料
| 型號(hào)： | NBSG14MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DATA BUFF 1:4 12GHZ 16QFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 扇出緩沖器（分配），數(shù)據(jù) |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVCMOS，LVDS，LVTTL，NECL，PECL，RSECL |
| 輸出： | RSECL，RSNECL，RSPECL |
| 頻率 - 最大： | 12GHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | NBSGOS14MNR2GOS |
NBSG14
http://onsemi.com
2
Figure 1. BGA16 Pinout (Top View)
VTCLK
CLK
VEE
VTCLK
Q0
VEE
Q3
Q2
VCC
Q0
Q1
Q2
A
B
C
D
12
3
4
VEE Q3
Q3 VCC
VEE Q0
Q0
VCC
Q1
Q2
VTCLK
CLK
VTCLK
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG14
Exposed Pad (EP)
Figure 2. QFN16 Pinout (Top View)
Table 1. Pin Description
Pin
Name
I/O
Description
BGA
QFN
D1
1
VTCLK
Internal 50 W Termination pin. See Table 2.
C1
2
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC.
B1
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75 kW to VEE.
A1
4
VTCLK
Internal 50 W Termination Pin. See Table 2.
B2,C2
5,16
VEE
Negative Supply Voltage. All VEE Pins must be Externally Connected to Power
Supply to Guarantee Proper Operation.
A2*
6
Q3
RSECL Output
Inverted Differential Output 3. Typically Terminated with 50 W to VTT = VCC 2 V*
A3*
7
Q3
RSECL Output
Noninverted Differential Output 3. Typically Terminated with 50 W to
VTT = VCC 2 V*
B3,C3
8,13
VCC
Positive Supply Voltage. All VCC Pins must be Externally Connected to Power
Supply to Guarantee Proper Operation.
A4*
9
Q2
RSECL Output
Inverted Differential Output 2. Typically Terminated with 50 W to VTT = VCC 2 V*
B4*
10
Q2
RSECL Output
Noninverted Differential Output 2. Typically Terminated with 50 W to
VTT = VCC 2 V*
C4*
11
Q1
RSECL Output
Inverted Differential Output 1. Typically Terminated with 50 W to VTT = VCC 2 V*
D4*
12
Q1
RSECL Output
Noninverted Differential Output 1. Typically Terminated with 50 W to
VTT = VCC 2 V*
D3*
14
Q0
RSECL Output
Inverted Differential Output 0. Typically Terminated with 50 W to VTT = VCC 2 V*
D2*
15
Q0
RSECL Output
Noninverted Differential Output 0. Typically Terminated with 50 W to
VTT = VCC 2 V*
N/A
EP
The Exposed Pad (EP) and the QFN16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heatsinking conduit. The pad is not electrically connected to the die
but may be electrically and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, if no
signal is applied then the device will be susceptible to selfoscillation.
*Devices in BGA package typically terminated with 50 W to VTT = VCC 1.5 V.
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