VCC = 0 V; V
參數(shù)資料
型號(hào): NBSG14BAR2
廠商: ON Semiconductor
文件頁(yè)數(shù): 13/13頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK/DATA BUFFER 1:4 16FCBGA
產(chǎn)品變化通告: Product Discontinuation 20/Aug/2008
標(biāo)準(zhǔn)包裝: 1
類型: 扇出緩沖器(分配),數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,LVCMOS,LVDS,LVTTL,NECL,PECL,RSECL
輸出: RSECL,RSNECL,RSPECL
頻率 - 最大: 12GHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-LBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 16-FCBGA(4x4)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: NBSG14BAR2OSDKR
NBSG14
http://onsemi.com
9
Table 9. AC CHARACTERISTICS for QFN16
VCC = 0 V; VEE = 3.465 V to 2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 4) (Note 29)
10.5
12
10.5
12
10.5
12
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
90
125
160
90
125
160
90
125
160
ps
tSKEW
Duty Cycle Skew (Note 30)
WithinDevice Skew (Note 31)
DevicetoDevice Skew (Note 32)
3
6
25
15
50
3
6
25
15
50
3
6
25
15
50
ps
tJITTER
RMS Random Clock Jitter
(Figure 4) (Note 34)
fin < 10 GHz
PeaktoPeak Data Dependent Jitter
(Note 35)
fin < 10 Gb/s
0.2
1
0.2
10
1
0.2
1
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 33)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times
Q, Q
(20% 80%) @ 1 GHz
15
30
55
20
30
55
20
30
55
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
29.Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC 2.0 V. Input edge rates 40 ps
(20% 80%)
30.See Figure 6. tSKEW = |tPLH tPHL| for a nominal 50% Differential Clock Input Waveform.
31.WithinDevice skew is measured between outputs under identical transitions and conditions on any one device.
32.Devicetodevice skew for identical transitions at identical VCC levels.
33.VINPP (MAX) cannot exceed VCC VEE (applicable only when VCCVEE < 2600 mV).
34.Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz.
35.Additive PeaktoPeak data dependent jitter with NRZ PRBS 2311 data at 10 Gb/s.
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