VCC = 0 V; V<" />
參數(shù)資料
型號: NBSG11MNR2G
廠商: ON Semiconductor
文件頁數(shù): 11/12頁
文件大小: 0K
描述: IC CLOCK BUFFER 1:2 12GHZ 16-QFN
標準包裝: 3,000
類型: 扇出緩沖器(分配)
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
輸入: CML,LVCMOS,LVDS,LVTTL,NECL,RSNECL,PECL
輸出: RSECL,RSNECL,RSPECL
頻率 - 最大: 12GHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 帶卷 (TR)
其它名稱: NBSGOS11MNR2GOS
NBSG11
http://onsemi.com
8
Table 8. AC CHARACTERISTICS for FCBGA16
VCC = 0 V; VEE = 3.465 V to 2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
40°C
25°C
70°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 4. Fmax/JITTER) (Note 22)
10.709
12
10.709
12
10.709
12
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
90
125
160
90
125
160
90
125
160
ps
tSKEW
Duty Cycle Skew (Note 23)
WithinDevice Skew (Note 24)
DevicetoDevice Skew (Note 25)
3
6
25
15
50
3
6
25
15
50
3
6
25
15
50
ps
tJITTER
RMS Random Clock Jitter
fin < 10 GHz
PeaktoPeak Data Dependent Jitter
fin < 10 Gb/s
0.2
10
1
0.2
10
1
0.2
10
1
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 26)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times
Q, Q
(20% 80%) @ 1 GHz
20
30
55
20
30
55
20
30
55
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
22.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 1.5 V for BGA package. For minimum fmax
value of 10.709 GHz, output amplitude is approximately 200 mV (as shown in Figure 4, where output PP spec is shown as a
minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% 80%).
23.See Figure 5. tSKEW = |tPLH tPHL| for a nominal 50% Differential Clock Input Waveform.
24.WithinDevice skew is defined as identical transitions on similar paths through a device.
25.Devicetodevice skew for identical transitions at identical VCC levels.
26.VINPP (MAX) cannot exceed VCC VEE.
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