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參數(shù)資料
| 型號(hào)： | NB7VQ14MMNG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 1:4 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 123 |
| 系列： | GigaComm™ |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | CML |
| 頻率 - 最大： | 8.5GHz |
| 電源電壓： | 1.71 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 管件 |
NB7VQ14M
http://onsemi.com
3
EQEN Q3
Q3 VCC
GND Q0
Q0
VCC
Q1
Q2
IN
VT
VREFAC
IN
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7VQ14M
Exposed Pad (EP)
Figure 2. QFN16 Pinout (Top View)
Table 1. EQUALIZER ENABLE FUNCTION
EQEN
Function
0
IN / IN Inputs Bypass the Equalizer section
1
Inputs flow through the Equalizer
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IN
LVPECL, CML,
LVDS Input
Noninverted Differential Input. Note 1.
2
VT
Internal 100 W Centertapped Termination Pin for IN / IN
3
VREFAC
Output Voltage Reference for CapacitorCoupled Inputs, only
4
IN
LVPECL, CML,
LVDS Input
Inverted Differential Input. Note 1.
5
EQEN
LVCMOS Input
Equalizer Enable Input; pin will default LOW when left open (has internal pulldown resistor)
6
Q3
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
7
Q3
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
8
VCC
Positive Supply Voltage
9
Q2
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
10
Q2
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
11
Q1
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
12
Q1
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
13
VCC
Positive Supply Voltage
14
Q0
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
15
Q0
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
16
GND
Negative Supply Voltage
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heatsinking
conduit. The pad is electrically connected to the die, and must be electrically and thermally con-
nected to GND on the PC board.
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
is applied on IN / IN input, then, the device will be susceptible to selfoscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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