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參數(shù)資料
| 型號： | NB7VQ1006MMNG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER RECEIVER 24-QFN |
| 標準包裝： | 92 |
| 邏輯類型： | 均衡器接收器 |
| 電源電壓： | 1.71 V ~ 2.625 V |
| 位數(shù)： | 1 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 24-QFN（4x4） |
| 包裝： | 管件 |
NB7VQ1006M
http://onsemi.com
6
Symbol
Characteristic
Min
Typ
Max
Unit
fDATA
Maximum Operating Input Data Rate
10
Gbps
fMAX
Maximum Input Clock Frequency
VCC = 2.5V
VCC = 1.8V
7.5
6.5
GHz
VOUTPP Output Voltage Amplitude EQEN = 0 or 1
fin v 5.0 GHz VCC = 2.5V
(See Figures 4, Note 9)
fin v 7.5 GHz VCC = 2.5V
fin v 5 GHz VCC = 1.8V
fin v 6.5 GHz VCC = 1.8V
275
225
200
440
360
315
mV
VCMR
Input Common Mode Range (Differential Configuration, Note 10) (Figure 8)
1050
VCC 50
mV
tPLH,
tPHL
Propagation Delay to Output Differential, IN/IN to Qn/Qn
170
225
315
ps
tPLH TC Propagation Delay Temperature Coefficient 40°C to +85°C
30
fs/°C
tDC
Output Clock Duty Cycle
48
50
52
%
tSKEW
Duty Cycle Skew (Note 11)
Within Device Skew (Note 12)
Device to Device Skew (Note 13)
0.15
10
20
1
25
40
ps
tJITTER
5 GHz v fin v 7.5 GHz
Deterministic Jitter (DJ) (Note 15) EQEN = 1, FR4 = 12”, v10 Gbps
VCC = 2.5 V
VCC = 1.8 V
0.2
3
0.7
1.2
40
20
ps
VINPP
Input Voltage Swing (Differential Configuration) (Note 16) (Figure 6)
100
1200
mV
tr, tf
Output Rise/Fall Times Qn/Qn, (20% 80%)
30
65
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured using a 400 mV source, 50% duty cycle 1GHz clock source. All outputs must be loaded with external 50 W to VCCO. Input edge
rates 40 ps (20% 80%).
9. Output voltage swing is a singleended measurement operating in differential mode.
10.VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ @ 5 GHz.
12.Within device skew compares coincident edges.
13.Device to device skew is measured between outputs under identical transition
14.Additive CLOCK jitter with 50% duty cycle clock signal.
15.Additive PeaktoPeak jitter with input NRZ data at PRBS23.
16.Input voltage swing is a singleended measurement operating in differential mode, with minimum propagation change of 25 ps.
Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input
Frequency (fin) at Ambient Temperature (Typ), (EQEN = 0)
fIN, CLOCK INPUT FREQUENCY (GHz)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
500
450
400
350
300
250
012
8
7
6
5
4
3
Figure 4. Input Structure
50 W
VT
VCC
IN
Q Output Amplitude (mV) VCC = 2.5 V
Q Output Amplitude (mV) VCC = 1.8 V
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