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參數(shù)資料
型號(hào): NB7VPQ16MMNTXG
廠商: ON Semiconductor
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 0K
描述: IC COPPER/CABLE DVR PROG 16-QFN
標(biāo)準(zhǔn)包裝: 3,000
邏輯類型: CML 驅(qū)動(dòng)器,帶可選均衡器接收器
電源電壓: 1.71 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 帶卷 (TR)
NB7VPQ16M
http://onsemi.com
4
Figure 4. Pin Configuration (Top View)
V
CCD
SDOUT
SCLKOUT
GND
V
CC
SDIN
SCLKIN
SLOAD
VCC
Q
VCC
VT
IN
GND
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7VPQ16M
Exposed Pad (EP)
Table 3. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VT
Internal 50W Termination Pin for IN and IN
2
IN
LVPECL, CML,
LVDS Input
Noninverted Differential Clock/Data Input. (Note 1)
3
IN
LVPECL, CML,
LVDS Input
Inverted Differential Clock/Data Input. (Note 1)
4
GND
Negative Supply Voltage; (Note 2)
5
VCCD
Positive Supply Voltage for Serial Bus Logic and 5Bit DAC; (Note 2)
6
SDOUT
LVCMOS
Output
Serial Data Out
7
SCLKOUT
LVCMOS
Output
Serial Clock Out
8
GND
Negative Supply Voltage; (Note 2)
9
VCC
Positive Supply Voltage for the analog circuitry and CML Output buffer; (Note 2)
10
Q
CML
Inverted Differential Output. (Note 1)
11
Q
CML
Noninverted Differential Output. (Note 1)
12
VCC
Positive Supply Voltage for the analog circuitry and CML Output buffer; (Note 2)
13
SLOAD
LVCMOS Input
When the SLOAD pin is LOW or left open (has internal pulldown resistor), the output of
the shift register will input the 4bit DAC and set the EQEN bit. When HIGH, the input to
the 4bit DAC is locked to the state prior to when SLOAD went HIGH.
14
SCLKIN
LVCMOS Input
Serial Clock In; pin will default LOW when left open (has internal pulldown resistor)
15
SDIN
LVCMOS Input
Serial Data In; pin will default LOW when left open (has internal pulldown resistor)
16
VCC
Positive Supply Voltage for the analog circuitry and CML Output buffer; (Note 2)
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat
sinking conduit. The pad is also electrically connected to the die, and must be electrically
and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no input
signal is applied on IN/IN input, then the device will be susceptible to selfoscillation. Q/Q outputs have internal 50 W source termination
resistor.
2. All VCC, VCCD and GND pins must be externally connected to a power supply voltage to guarantee proper device operation.
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